Sharp XL-MP100H

XL-MP100H
8 – 8
IC801 VHIMN6627933C: CD Digital Signal Processor (MN6627933C)
STAT* MLD MDATA MCLK EXT2 * EXT1 * EXT0 * DVS S 2 DVDD3 TMON2 NC NC TMON1 NC LOVDD1 LOOUTR LOVSS1 LOOUTL AVSS PLLFO PLLF PWMSEL DSLF ARF IREF
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
BLKCK * 76 50 AVDD
SMCK * 77 49 BDO
PMCK * 78 48 OFT
TX * 79 47 NRFDET
FLAG * 80 46 LDON
NRST 81 45 RFENV
NTEST 8 2 44 ADPVCC
DVSS3 83 43 TE
X1 84 42 FE
X2 85 41 FBAL
IOVDD2 86 40 TBAL
DVDD2 87 3 9 IOVDD1
D2 88 38 FOM *
D1 89 37 FOP
D0 90 36 TRM *
D3 91 35 TRP
D4 92 34 TRVM2 *
D5 93 33 TRVP2 *
D6 94 32 TRVM *
D7 95 31 TRVP
D15 96 30 SPPOL *
D14 97 29 SPOUT
DRVDD2 98 28 DVDD1
D13 99 27 BA0 *
D12 100 26 BA1 *
1 2 3 4 5 6 7 8 910111213141516171819202122232425
D11 D10
D9 D8
UDQM
SDRCK
A11
A9 A8 A7 A6 A5 A4
LDQM
NWE
NCAS
NRAS
NCS
A3 A2 A1 A0
DRVDD
DVSS1
A10
MN6627933C
NTEST
NRST
ADPVCC
FE
TE
RFENV
OF
NRFDET
BDO
SPPO
PWMSE
SPOU
TRV
TRV
* TRVM
* T RV
TR
TR
TBA
FO
FO
FBA
LDO
*
*
*
*
* T
EX
EX
EX
*
*
*
TMO
TMO
T
L
L
T
P
M
2
P2
M
P
L
M
P
L
N
X
T0
T1
T2
N1
N2
TL
TR
LOVDD1 LOVSS1
KIN
(EXT
KIN
(EXT
SRDATIN
(EXT
LOOU LOOU
DVSS2 DVSS3 DVSS1 IOVDD1
IOVDD2
LRC
1)
BCL
2
)
0)
CIRC
EFM DEMODULATION
SYNC INTERPOLAT ION
CIRC ECC
CDROM ECC
BUS CONTROL UNIT
(BCU)
ADPCM
SERIAL OUTPUT
INTERFACE
MP3
DECORDER
FS
CONVERTER
SPINDLE
SERVO
SERVO
CPU
CONVERTER
INPUT PORT
A/D
OUTPUT
PORT
DIGITAL OUT
DIGITAL FILTE R
DAC
PWM LOGIC
ANALOG
LOWPASS
FILTER
REGULATER
DVDD
1bit
SUBCODE
INTERFACE
DRAM
INTERFACE
RAM
X1
X2
SMCK
PMCK
* S TAT
MLD
MCLK
MDATA
* *
TIMING
GENERATOR
MICRO COMPUTER
INTERFACE
DS PLL VCO
ARF
IREF
DSLF
PLLF
PLLFO
AVSS
AVDD
L
TXTCK
(EXT1)
TXTD
(EXT0)
DQSY_TXT
(EXT2)
SBCK
(EXT1)
SUBC
(EXT0)
TXNCLDCK
(EXT2)
FLAG*
BLKCK*
A11~A0
D15~D0
NCAS
NRAS
NWE
NCS
SDRCK
* BA0
* BA1
UDQM
LDQM
DRVDD1
DRVDD2
LRCK(EXT1)
BCLK(EXT2)
SRDATA
(EXT0)
Figure 7 BLOCK DIAGRAM OF IC