Siemens A70 - Battery

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Copyright 2005© Siemens AG
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TD_Repair_L2.5_A70_A75_R1.0.pdf Release 1.0
Functions Pin Requirements Implementation/Sequence
I2S Interface CLO,
WAO,
DAO
The I2S Interface is a three wire connection that handels two
timemultiplexed data channels. The three lines are the clock
(CLO), the serial data line (DAO) and the word select line
(WAO). The master I2S also generates the appropriate clock
frequncy for CLO set to 32 times the sampling rate (FS)
Audio DAC VDDDAC For digital to analog conversion a 16 bit sigma delta converter
is used. Digital input signal is delivered with a I2S interface.
The I2S interface should be 16 bit format. To be able to work
with allpossible operating modes, the sampling frequency can
vary from 8kHz to 48kHz. The performance of the audio
output signal must be guaranteed over the full range the
human ear is able to hear. This means for FS=8kHz the noise
at frequencies higher than FS/2 must be suppressed. This is
done by DSP in a single ended 2
nd
order Low Pass filter. The
clock for the I2S will be varied accordingly to the sampling
frequency. Therefore a clock recovery based on CLO signal
of the I2S can be implemented. This clock recovery must
smooth any jitter of this clock to reduce the noise of the DAC.
PLL VDDPLL
PLLOUT
The PLL will have three frequency modes to produce a
32xCLO clock for the DSP and the DAC. The loop filter is
realised with an external RC circuit. This PLL also contains a
lock detector circuit.
9.2 Battery
As a standard battery a LiIon battery with a nominal capacity of 3,7 Volt/700mAh is used.