Siemens CPU 414-2 - Page 29

Bit Logic Instructions
27
S7-400 Instruction List
A5E00267845-01
Bit Logic Instructions, continued
Instr.
Address-
Description
Lengt
h in
Execution Time in s
Instr.
Address-
ID
Description
Lengt
h in
Words
Execution Time in

s
h in
Words
CPU 412 CPU 414 CPU 416 CPU 417
X/XN
E/A a.b
M a.b
L a.b
DBX a.b
DIX a.b
c [d]
c [AR1,m]
c [AR2,m]
[AR1,m]
[AR2,m]
Parameter
EXKLUSIV-OR/
EXKLUSIV-OR-NOT
Input/output
Bit memory
Local data bit
Data bit
Instance data bit
Memory-indirect, area-internal.
*)
Register-ind., area-internal (AR1)
*)
Register-ind., area-internal (AR2)
*)
Area-crossing (AR1)
*)
Area-crossing (AR2)
*)
Via parameter
*)
2
2
2
2
2
2
2
2
2
2
2
0.125
0.125
0.125
0.2
0.2
0.1+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.125+/0.2+
0.075
0.075
0.075
0.12
0.12
0.06+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.075+/0.12+
0.05
0.05
0.05
0.08
0.08
0.04+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+
0.05+/0.08+
0.042
0.042
0.042
0.09
0.09
0.03+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
0.042+/0.09+
Status word for: X, XN BR CC1 CC0 OV OS OR STA RLO /FC
Instruction evaluates: – – – – – – – Yes Yes
Instruction affects: – – – – – 0 Yes Yes 1
+Plus time required for loading the address of the instruction (see page 20)
*)
I,Q,M,L / DB, DI