Siemens CPU 414-2 - Page 57

Transfer Instructions
55
S7-400 Instruction List
A5E00267845-01
Transfer Instructions, continued
If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this
page are doubled.
Instruc-
Length
Execution Time in s
Instruc-
tion
Address
Description
Length
in
Execution Time in

s
tion
Address
ID
Description
in
Words
CPU 412 CPU 414 CPU 416 CPU 417
T
IW a
QW a
PQW a
Transfer contents of ACCU1-L to ...
input word
output word
peripheral output word
2)
1
1)
/2
1
1)
/2
1
1)
/2
0.1/0.125
0.1/0.125
0.1/0.125
0.06/0.075
0.06/0.075
0.06/0.075
0.04/0.05
0.04/0.05
0.04/0.05
0.03/0.042
0.03/0.042
0.03/0.042
MW a
LW a
bit memory word
local data word
1
3)
/2
2
0.1/0.125
0.125
0.06/0.075
0.075
0.04/0.05
0.05
0.03/0.042
0.042
DBW a
DIW a
data word
instance data word
2
2
0.335
0.335
0.075
0.075
0.05
0.05
0.042
0.042
h [d]
h [AR1,m]
h [AR2,m]
W[AR1,m]
W[AR2,m]
Parameter
Memory-indirect, area internal
Register-ind., area internal (AR1)
Register-ind., area internal (AR2)
Area-crossing (AR1)
Area-crossing (AR2)
Via parameter
2
2
2
2
2
2
0.1+
0.125+
0.125+
0.125+
0.125+
0.125+
0.06+
0.075+
0.075+
0.075+
0.075+
0.075+
0.04+
0.05+
0.05+
0.05+
0.05+
0.05+
0.03+
0.042+
0.042+
0.042+
0.042+
0.042+
+ Plus time required for loading the address of the instruction (see page 20)
1)
With direct instruction addressing; Address area 0 to 127
2)
The following peripheral acknowledgement time must be observed with CPU 414-4H and CPU 417-4H: solo xx s, redundant xx s
3)
With direct instruction addressing; Address area 0 to 255