xiv
S7-300, Installation and Hardware
EW
A 4NEB 710 6078-02a
7-8 Cable
Lengths in an MPI Subnet
7-17.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-9 Bus
Connectors 6ES7 ... : T
erminating Resistor Activated and
Deactivated 7-22.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7-10 Removing
the Slide on the RS 485 Repeater
7-23.
. . . . . . . . . . . . . . . . . . . . . . .
7-11 Lengths
of the Stripped Insulation for Connection to the RS 485 Repeater
7-24
8-1
Plugging the Memory Card into the CPU
8-3.
. . . . . . . . . . . . . . . . . . . . . . . . . . .
8-2 Inserting
a Backup Battery in the CPUs 313/314
8-5.
. . . . . . . . . . . . . . . . . . . .
8-3 Connecting
a Programming Device to an S7-300
8-7.
. . . . . . . . . . . . . . . . . . . .
8-4 Connecting
a Programming Device with Several S7-300s
8-8.
. . . . . . . . . . . .
8-5 Connecting
a Programming Device to a Subnet
8-9.
. . . . . . . . . . . . . . . . . . . . .
8-6 Programming
Device Connected to an Ungrounded S7-300
8-10.
. . . . . . . . . .
8-7 Switching
Sequence for the Mode Selector for Resetting the CPU
8-12.
. . . . .
9-1 Changing
the Backup Battery in the CPUs 313/314
9-2.
. . . . . . . . . . . . . . . . . .
9-2 Unlocking
the Front Connector and Detaching the Module from the Rail
9-5.
9-3 Removing
the Front Connector Coding Key
9-6.
. . . . . . . . . . . . . . . . . . . . . . . .
9-4 Installing
a New Module
9-6.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-5 Plugging
In the Front Connector
9-7.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-6 Location
of the Fuses on Digital Output Modules
9-9.
. . . . . . . . . . . . . . . . . . . .
10-1 Status
and Fault LEDs on the CPUs
10-6.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-2 Principle
of Forcing with S7-300 CPUs
10-8.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-3 Clock
Periods in the ”Clock Memory Byte”
10-22.
. . . . . . . . . . . . . . . . . . . . . . . . . .
10-4 Signalling
the Status of the Interrupt Inputs of the Integrated I/O
10-33.
. . . . . . .
10-5 Elements
of the CPU 312 IFM
10-36.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-6 Terminal
Connections of the CPU 312 IFM
10-41.
. . . . . . . . . . . . . . . . . . . . . . . . .
10-7 Basic
Circuit Diagram of the CPU 312 IFM
10-42.
. . . . . . . . . . . . . . . . . . . . . . . . .
10-8 Elements
of the CPU 313
10-44.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-9 Elements
of the CPU 314
10-47.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-10 Elements
of the CPU 314 IFM
10-50.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-11 Terminal
Connections of the CPU 314 IFM
10-59.
. . . . . . . . . . . . . . . . . . . . . . . . .
10-12 Basic
Circuit Diagram of the CPU 314 IFM (Special Inputs and Analog
Inputs and Outputs)
10-60.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-13 Basic
Circuit Diagram of the CPU 314 IFM (Digital Inputs and Outputs)
10-61.
10-14 Elements
of the CPU 315
10-63.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-15 Elements
of the CPU 315-2 DP
10-67.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-16 Elements
of the CPU 316
10-70.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-1 Intermediate
Memory in the DP Slave CPU 315-2 DP
11-7.
. . . . . . . . . . . . . . . .
11-2 Diagnostic
Addresses for DP Master and DP Slave
11-13.
. . . . . . . . . . . . . . . . . .
11-3 Format
of the Slave Diagnostic Data
11-17.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-4 Format
of the Identifier-Related Diagnostic Data
11-21.
. . . . . . . . . . . . . . . . . . . .
11-5 Format
of the Device-Related Diagnostic Data
11-22.
. . . . . . . . . . . . . . . . . . . . . .
11-6 Bytes
13 to 16 for Diagnostic and Process Interrupts
11-23.
. . . . . . . . . . . . . . . .
11-7 Standardized
Portion of the Parameter Assignment Frame (example)
11-25.
. .
11-8 Parameters
for the CPU 315-2 DP
11-26.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11-9 Description
of Byte 0 of the CPU’
s Address Area Identifiers
11-28.
. . . . . . . . . . .
11-10 Description
of Byte 1 of the CPU’
s Address Area Identifiers
11-28.
. . . . . . . . . . .
12-1 Component
Parts of the Cycle T
ime 12-2.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-2 Shortest
Response T
ime 12-5.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-3 Longest
Response T
ime 12-6.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-4 Overview
of the Bus Runtime on PROFIBUS-DP at 1.5 Mbit/s and
12 Mbit/s
12-10.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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