18.3.2.12 2x Count Mode
When the timer is set in 2x mode, the TIMER will count up/down by two. This will in effect make any odd Top value be rounded down to
the closest even number. Similarly, any odd CC value will generate a match on the closest lower even value as shown in Figure
18.34 TIMER CC out in 2x mode on page 595
2 4 2 0 20
Clock
CC Out
4
2 4 2 0 20
4
Top = 5
CC = 1
Top = 5
CC = 2
Figure 18.34. TIMER CC out in 2x mode
Figure 18.35 TIMER 2x PWM Resolution Equation on page 595.
R
PWM
2xmode
= log(TOP/2+1)/log(2)
Figure 18.35. TIMER 2x PWM Resolution Equation
The PWM frequency is given by Figure 18.36 TIMER 2x Mode PWM Frequency Equation( Up/Down-count) on page 595:
f
PWM
2xmode
= f
HFPERCLK
/ (floor(TOP/2)*2)
Figure 18.36. TIMER 2x Mode PWM Frequency Equation( Up/Down-count)
The high duty cycle is given by two equations based on the CCVx values.Figure 18.37 TIMER 2x Mode Duty Cycle Equation for CCVx
= 1 or CCVx = even on page 595 and Figure 18.38 TIMER 2x Mode Duty Cycle Equation for all other CCVx = odd values on page
595
DS
2xmode
= (CCVx*2)/(floor(TOP/2)*4)
Figure 18.37. TIMER 2x Mode Duty Cycle Equation for CCVx = 1 or CCVx = even
DS
2xmode
= (CCVx*2 - CCVx)/(floor(TOP/2)*4)
Figure 18.38. TIMER 2x Mode Duty Cycle Equation for all other CCVx = odd values
18.3.2.13 Timer Configuration Lock
To prevent software errors from making changes to the timer configuration, a configuration lock is available similar to DTI configuration
Lock. Writing any value but 0xCE80 to LOCKKEY in TIMERn_LOCK results in TIMERn_CTRL, TIMERn_CMD, TIMERn_TOP,
TIMERn_CNT, TIMERn_CCx_CTRL and TIMERn_CCx_CCV being locked from writing. To unlock the registers, write 0xCE80 to LOCK-
KEY in TIMERn_LOCK. The value of TIMERn_LOCK is 1 when the lock is active, and 0 when the registers are unlocked.
EFM32JG1 Reference Manual
TIMER - Timer/Counter
silabs.com | Smart. Connected. Energy-friendly. Preliminary Rev. 0.6 | 595
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