Silicon Laboratories Si5328

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Summary

3. Any-Frequency Clock Family Members

3.1. Si5316

Details the Si5316 as a low jitter, precision jitter attenuator for high-speed communication systems.

3.5. Si5324

Describes the Si5324 as a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance.

3.9. Si5328

Describes the Si5328 as a jitter-attenuating precision clock multiplier for applications requiring sub-1 ps jitter performance.

3.16. Si5374

Details the Si5374 as a highly integrated, 4-PLL jitter-attenuating precision clock multiplier.

4. DSPLL (All Devices)

4.1. Clock Multiplication

Explains the clock multiplication circuit fundamental to the devices and the role of software tools.

4.2. PLL Performance

Discusses PLL performance aspects including jitter generation and jitter transfer.

4.2.3. Jitter Tolerance

Defines jitter tolerance as the maximum input jitter before the DSPLL loses lock.

5. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

5.2. PLL Self-Calibration

Explains internal self-calibration for optimizing loop parameters and jitter performance.

5.3. Pin Control Input Clock Control

Describes clock selection capabilities: manual, auto, hitless, and revertive switching.

5.4. Digital Hold;VCO Freeze

Explains holdover or VCO freeze mode, locking the DSPLL to a digital value.

6. Microprocessor Controlled Parts

6.1. Clock Multiplication

Explains setting input frequency, multiplication ratio, and output frequency via register settings.

6.2. PLL Self-Calibration

Explains the device performs internal self-calibration before operation.

6.6. Digital Hold

Explains the device's holdover mode where the DSPLL is locked to a digital value.

6.11. Alarms

Summarizes alarms indicating input signal status and frame alignment.

6.13. I2 C Serial Microprocessor Interface

Explains the 2-wire bus for bidirectional communication using SDA and SCL lines.

6.14. Serial Microprocessor Interface (SPI)

Describes the 4-wire interface for microcontroller and serial peripheral communication.

7. High-Speed I;O

7.1. Input Clock Buffers

Details differential inputs for CKINn clock inputs, bias voltage, and AC coupling.

7.2. Output Clock Drivers

Explains output clock configuration for compatibility with LVPECL, CML, LVDS, or CMOS.

7.4. Crystal;Reference Clock Interfaces

Details interfaces for crystal or external clock references, including specific device limitations.

Appendix A-NARROWBAND REFERENCES

Reference Source Selection

Details how the Si53xx reference source is determined by the device RATE[1:0] pin settings.

Appendix B-FREQUENCY PLANS AND TYPICAL JITTER PERFORMANCE

High f3 Value

Explains f3 definition, its range, and its impact on jitter performance.

Appendix J-Si5374, Si5375, AND Si5376 PCB LAYOUT RECOMMENDATIONS

RSTL_x Pins

Recommends logically connecting RSTL_x pins for consistent reset behavior across DSPLLs.