Silicon Laboratories SI5351A/B/C - User Manual

Preliminary Rev. 0.95 8/11 Copyright © 2011 by Silicon Laboratories Si5351A/B/C
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5351A/B/C
I
2
C-PROGRAMMABLE ANY-FREQUENCY CMOS CLOCK
GENERATOR + VCXO
Features
Applications
Description
The Si5351 is an I
2
C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 160 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. The Si5351B eliminates the need for higher cost, custom pullable
crystals while providing reliable operation over a wide tuning range. The Si5351C offers
the same flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
 Generates up to 8 non-integer-related
frequencies from 8 kHz to 160 MHz
 I
2
C user definable configuration
 Exact frequency synthesis at each output
(0 ppm error)
 Highly linear VCXO
 Optional clock input (CLKIN)
 Low output period jitter: 100 ps pp
 Configurable spread spectrum selectable
at each output
 Operates from a low-cost, fixed frequency
crystal: 25 or 27 MHz
 Supports static phase offset
 Programmable rise/fall time control
 Glitchless frequency changes
 Separate voltage supply pins:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
 Excellent PSRR eliminates external
power supply filtering
 Very low power consumption
 Adjustable output-output delay
 Available in 3 packages types:
10-MSOP: 3 outputs
24-QSOP: 8 outputs
20-QFN (4x4 mm): 8 outputs
 PCIE Gen 1 compliant
 Supports HCSL compatible swing
 HDTV, DVD/Blu-ray, set-top box
 Audio/video equipment, gaming
 Printers, scanners, projectors
 Residential gateways
 Networking/communication
 Servers, storage
 XO replacement
Si5351A
Multi
Synth
N
N = 2 or 7
I
2
C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Si5351B
PLL
VC
VCXO
I
2
C
SSEN
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
Si5351C
PLLA
CLKIN
PLLB
I
2
C
INTR
OEB
Multi
Synth
0
Multi
Synth
1
Multi
Synth
2
Multi
Synth
3
Multi
Synth
4
Multi
Synth
5
Multi
Synth
6
Multi
Synth
7
XA
XB
OSC
XA
XB
OSC
PLLB
PLLA
XA
XB
OSC
Ordering Information:
See page 66
10-MSOP
24-QSOP
20-QFN

Summary

Electrical Specifications

Functional Description

Input Stage

Describes the device's input stage, including crystal and clock inputs.

Synthesis Stages

Explains the two synthesis stages and their flexibility.

Output Stage

Details the output stage, including division and output drivers.

Spread Spectrum

Covers the spread spectrum feature for EMI reduction.

Control Pins (OEB, SSEN)

Explains the function of OEB and SSEN control pins.

I2 C Interface

Configuring the Si5351

Writing a Custom Configuration to RAM

Details the process of writing custom configurations via I2C.

Design Considerations

Power Supply Decoupling;Filtering

Guidelines for power supply decoupling and filtering.

Power Supply Sequencing

Recommendations for power supply sequencing for VDD and VDDOx.

External Crystal

Guidance on mounting and routing external crystals.

External Crystal Load Capacitors

Information on using internal and external load capacitors.

Unused Pins

Specifies how to handle unused pins.

Trace Characteristics

Recommendations for trace characteristics with 8 mA drive strength.

Register Descriptions

Register 0. Device Status

Describes bits related to device initialization and PLL status.

Register 1. Interrupt Status Sticky

Defines sticky bits for system and lock status interrupts.

Register 2. Interrupt Status Mask

Controls masking of interrupt status bits.

Register 3. Output Enable Control

Controls the enable/disable state of individual clock outputs.

Register 15. PLL Input Source

Selects the input source for PLLB and PLLA.

Register 165. CLK0 Initial Phase Offset

Configures the initial phase offset for Clock 0.

Pin Descriptions

Si5351 A Pin Descriptions (20-Pin QFN, 24-Pin QSOP)

Details pins for Si5351A in 20-QFN and 24-QSOP packages.

Si5351 B Pin Descriptions (20-Pin QFN, 24-Pin QSOP)

Details pins for Si5351B in 20-QFN and 24-QSOP packages.

Si5351 C Pin Descriptions (20-Pin QFN, 24-Pin QSOP)

Details pins for Si5351C in 20-QFN and 24-QSOP packages.

Si5351 A Pin Descriptions (10-Pin MSOP)

Details pins for Si5351A in the 10-MSOP package.

Package Outline

Package Outline (24-Pin QSOP)

Mechanical dimensions for the 24-QSOP package.

Package Outline (20-Pin QFN)

Mechanical dimensions for the 20-Pin QFN package.

Package Outline (10-Pin MSOP)

Mechanical dimensions for the 10-Pin MSOP package.

Silicon Laboratories SI5351A/B/C Specifications

General

Brand	Silicon Laboratories
Model	SI5351A/B/C
Category	Computer Hardware
Language	English