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Silicon Laboratories Si5345 User Manual
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Rev. 1.0 7/16
Copyright © 2016 by Si
licon Laborato
ries
Si5345-44-42-D-RM
A
NY
-F
REQUENCY
, A
NY
-O
UTPUT
J
ITTER
-A
TTENUATORS
/C
LOCK
M
ULTIPLIERS
Si5345, Si5344, Si5342 R
EV
. D
F
AMILY
R
EFERENCE
M
ANUAL
2
Table of Contents
Default Chapter
2
Table of Contents
2
1 Scope
9
Related Documents
9
2 Overview
9
Work Flow Expectations with Clockbuilder Pro™ and the Register Map
9
Family Product Comparison
9
Table 1. Product Selection Guide
9
Available Software Tools and Support
10
Figure 1. Block Diagram Si5345/44/42
10
3 DSPLL and Multisynth
11
Figure 2. Si5342 DSPLL and Multisynth System Flow Diagram
11
Dividers
12
DSPLL Loop Bandwidth
12
Table 2. PLL_BW Registers
12
Fastlock Feature
13
Holdover Exit Bandwidth
13
Table 3. Fastlock Registers
13
Table 4. DSPLL Holdover Exit Bandwidth Registers
13
4 Modes of Operation
14
Reset and Initialization
14
Figure 3. Modes of Operation
14
Figure 4. Si5345/44/42 Memory Configuration
15
Figure 5. Initialization from Hard Reset and Soft Reset
15
Table 5. Reset Registers
15
Dynamic PLL Changes
16
Revision B and a
16
Revision D
16
NVM Programming
17
Free Run Mode
17
Acquisition Mode
17
Locked Mode
17
Table 6. NVM Programming Registers
17
Holdover Mode
18
Figure 6. Programmable Holdover Window
18
Table 7. Holdover Mode Control Registers
19
5 Clock Inputs
21
Inputs (IN0, IN1, IN2, IN3)
21
Manual Input Switching
21
Table 8. Input Selection Configuration
21
Table 9. Manual Input Selection Using IN_SEL[1:0] Pins
21
Automatic Input Selection
22
Table 10. Registers for Automatic Input Selection
22
Types of Inputs
23
Figure 7. Input Termination for Standard and Pulsed CMOS Inputs
23
Hitless Input Switching with Phase Buildout
24
Table 11. Register 0X0949 Clock Input Control and Configuration
24
Table 12. Hitless Switching Enable Bit
24
Unused Inputs
24
Glitchless Input Switching
25
Ramped Input Switching
25
Table 13. Ramped Input Switching Control Registers
25
Synchronizing to Gapped Input Clocks
26
Fault Monitoring
26
Figure 8. Generating an Averaged Non Gapped Output Frequency from a Gapped Input
26
Figure 9. Si5342/44/45 Fault Monitors
26
Figure 10. LOS Status Indicators
27
Input Loss of Signal (LOS) Fault Detection
27
Table 14. Loss of Signal Status Monitoring and Control Registers
27
Figure 11. OOF Status Indicator
28
Figure 12. Example of Precise OOF Monitor Assertion and De-Assertion Triggers
28
Out of Frequency (OOF) Fault Detection
28
Loss of Lock Fault Monitoring
29
Table 15. Out-Of-Frequency Status Monitoring and Control Registers
29
Figure 13. LOL Status Indicators
30
Figure 14. LOL Set and Clear Thresholds
30
Table 16. Loss of Lock Status Monitor and Control Registers
30
Interrupt Configuration
32
Figure 15. Interrupt Pin Source Masking Options
32
6 Output Clocks
33
Output Crosspoint Switch
33
Figure 16. Multisynth to Output Driver Crosspoint
33
Table 17. Output Driver Crosspoint Configuration Registers
34
Performance Guidelines for Outputs
35
Table 18. Example of Output Clock Frequency Sequencing Choice
35
Output Signal Format
36
Table 19. Output Signal Format Control Registers
36
Differential Output Swing Modes
37
Differential Output Terminations
37
Figure 17. Supported Differential Output Terminations
37
Figure 18. Vpp_Se and Vpp_Diff
37
Programmable Common Mode Voltage for Differential Outputs
38
Table 20. Differential Output Voltage Swing Control Registers
38
Table 21. Differential Output Common Mode Voltage Control Registers
38
Figure 19. LVCMOS Output Terminations
39
LVCMOS Output Impedance and Drive Strength Selection
39
LVCMOS Output Terminations
39
Table 22. Output Impedance and Drive Strength Selections
39
LVCMOS Output Signal Swing
40
Table 23. LVCMOS Drive Strength Control Registers
40
LVCMOS Output Polarity
41
Table 24. LVCMOS Output Polarity Control Registers
41
Table 25. Output Polarity of Outx and Outx Pins in LVCMOS Mode
41
Output Driver Settings for LVPECL, LVDS, HCSL, and CML
42
Table 26. Settings for LVDS, LVPECL, and HCSL
42
Output Enable/Disable
43
Table 27. Output Enable/Disable Control Registers
43
Output Driver State When Disabled
44
Synchronous Output Disable Feature
44
Table 28. Output Driver State Control Registers
44
Table 29. Synchronous Disable Control Registers
44
Output Skew Control (T0-T4)
45
Figure 20. Example of Independently-Configurable Path Delays
45
Output Buffer Supply Voltage Selection
46
Table 30. Output Delay Registers
46
Table 31. Outx VDD Settings
46
7 Zero Delay Mode
47
Figure 21. Si5345 Zero Delay Mode Set-Up
47
Table 32. Zero Delay Mode Registers
48
Table 33. Input Clock Selection in Zero Delay Mode
48
8 Digitally-Controlled Oscillator (DCO) Mode
49
DCO with Frequency Increment/Decrement Pins/Bits
49
Figure 22. DCO with FINC/FDEC Pins or Bits
50
DCO with Direct Register Writes
51
Table 34. Frequency Increment/Decrement Control Registers
51
9 Serial Interface
52
Figure 23. I2C/SPI Device Connectivity Configurations
52
Table 35. I2C/SPI Register Settings
52
Figure 24. I2C Configuration
53
Figure 25. 7-Bit I2C Slave Address Bit-Configuration
53
I2C Interface
53
Figure 26. I2C Write Operation
54
Figure 27. I2C Read Operation
54
Figure 28. SPI Interface Connections
55
SPI Interface
55
Table 36. Smbus Timeout Error Bit Indicators
55
Table 37. SPI Command Format
55
Figure 29. Example Writing Three Data Bytes Using the Write Commands
56
Figure 30. Example of Reading Three Data Bytes Using the Read Commands
57
Figure 31. SPI "Set Address" Command Timing
57
Figure 32. SPI "Write Data" and "Write Data+ Address Increment" Instruction Timing
58
Figure 33. SPI "Read Data" and "Read Data + Address Increment" Instruction Timing
59
Figure 34. SPI "Burst Data Write" Instruction Timing
59
10 Field Programming
60
11 XAXB External References
61
Performance of External References
61
Figure 35. Crystal Resonator and External Reference Clock Connection Options
61
Figure 36. Clipped Sine Wave TCXO Output
62
Figure 37. CMOS TCXO Output
62
Recommended Crystals
63
Table 38. Recommended Crystals
63
Figure 38. Maximum ESR Vs. C0 for 25 Mhz Crystal
65
Figure 39. Maximum ESR Vs. C0 for 48-54 Mhz Crystal
65
Recommended Oscillators
66
Register Settings to Control External XTAL Reference
66
XAXB_FREQ_OFFSET Frequency Offset Register
66
XAXB_EXTCLK_EN Reference Clock Selection Register
66
Table 39. Recommended Oscillator Suppliers
66
Table 40. XAXB Frequency Offset Register
66
Table 41. XAXB External Clock Selection Register
66
PXAXB Pre-Scale Divide Ratio for Reference Clock Register
67
Table 42. Pre-Scale Divide Ratio Register
67
Table 43. Pre-Scale Divide Values
67
12 Crystal and Device Circuit Layout Recommendations
68
64-Pin QFN Si5345 Layout Recommendations
68
Si5345 Applications Without a Crystal
68
Si5345 Crystal Guidelines
68
Figure 40. 64-Pin Si5345 Crystal Layout Recommendations Top Layer (Layer 1)
69
Figure 41. Zoom View Crystal Shield Layer, below the Top Layer (Layer 2)
69
Figure 42. Crystal Ground Plane (Layer 3)
70
Figure 43. Power Plane (Layer 4)
70
Figure 44. Layer 5 Power Routing on Power Plane (Layer 5)
71
Figure 45. Ground Plane (Layer 6)
71
Output Clocks
72
Figure 46. Output Clock Layer (Layer 7)
72
Figure 47. Bottom Layer Ground Flooded (Layer 8)
72
44-Pin QFN Si5344/42 Layout Recommendations
73
Si5342/44 Applications Without a Crystal
73
Figure 48. Device Layer (Layer 1)
73
Si5342/44 Crystal Guidelines
74
Figure 49. Crystal Shield Layer 2
74
Figure 50. Ground Plane (Layer 3)
74
Figure 51. Power Plane and Clock Output Power Supply Traces (Layer 4)
75
Figure 52. Clock Input Traces (Layer 5)
75
Figure 53. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer)
76
13 Power Management
77
Power Management Features
77
Table 44. Power-Down Registers
77
Power Supply Recommendations
78
Power Supply Sequencing
78
Grounding Vias
78
14 Register Map
79
Base Vs. Factory Preprogrammed Devices
79
Base" Devices (A.k.a. "Blank" Devices)
79
Factory Preprogrammed" (Custom OPN) Devices
79
Register Map Overview and Default Settings Values
80
Table 45. Register Map Paging Descriptions
80
Si5345 Register Map
81
Registers Si5345
81
Figure 54. FINC, FDEC Logic Diagram
87
Registers Si5345
98
Table 46. Registers that Follow the same Definitions above
100
Registers Si5345
103
Table 47. Registers that Follow the P0_NUM and P0_DEN above
104
Table 48. Registers that Follow the R0_REG
107
Registers Si5345
111
Table 49. Registers that Follow the N0_NUM and N0_DEN Definitions
112
Figure 55. Logic Diagram of the FINC/FDEC Masks
113
Table 50. Registers that Follow the N0_FSTEPW Definitions
113
Registers Si5345
115
Registers Si5345
116
Registers Si5345
125
Page a Registers Si5345
127
Page B Registers Si5345
128
Si5344 Register Definitions
129
Registers Si5344
129
Figure 56. Logic Diagram of the FINC/FDEC Masks
134
Registers Si5344
145
Table 51. Registers that Follow the same Definitions above
147
Registers Si5344
150
Table 52. Registers that Follow the P0_NUM and P0_DEN
151
Table 53. Registers that Follow the R0_REG
154
Registers Si5344
157
Table 54. Registers that Follow the N0_NUM and N0_DEN Definitions
157
Table 55. Registers that Follow the N0_FSTEPW Definition
158
Registers Si5344
160
Registers Si5344
161
Registers Si5344
170
Page a Registers Si5344
172
Page B Registers Si5344
173
Si5342 Register Definitions
174
Registers Si5342
174
Figure 57. FINC, FDEC Logic Diagram
179
Registers Si5342
191
Table 56. Registers that Follow the same Definition as above
193
Registers Si5342
195
Table 57. Registers that Follow the P0_NUM and P0_DEN Definitions
196
Table 58. Registers that Follow the R0_REG
199
Registers Si5342
202
Table 59. Register that Follows the N0_NUM and N0_DEN Definitions
202
Table 60. Registers that Follow the N0_FSTEPW Definition
203
Table 61. Registers that Follow the N0_DELAY Definition
204
Registers Si5342
205
Registers Si5342
206
Registers Si5342
215
Page a Registers Si5342
217
Page B Registers Si5342
218
Appendix A-Setting the Differential Output Driver to
219
Non-Standard Amplitudes
219
Table 62. Output Differential Common Mode Voltage Settings
219
Table 63. Typical Differential Amplitudes
220
Document Change List
221
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Silicon Laboratories Si5345 Specifications
General
Brand
Silicon Laboratories
Model
Si5345
Category
Computer Hardware
Language
English
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