DRAFT D
TNM-M-E-0001 Page 19
3.3 Frequency Synthesiser
3.3.1 General
Refer Figure 3-3
The SRM9000 frequency synthesiser consists of individual transmitter and receiver (local
oscillator) voltage controlled oscillators, loop filter, varactor negative bias generator, reference
oscillator and an integrated, dual phase locked loop device U701.
3.3.2 PLL
The PLL device contains two prescalers, programmable dividers and phase comparators to
provide a main and auxiliary PLL. The main PLL of U701 controls the frequency of the TX/RX
VCOs via Control Voltage outputs at pins 2 and 3 and VCO Feedback to pin 6. The auxiliary
PLL is used to control the receiver 90MHz second local oscillator via the Control Voltage output
at pin 17 and VCO Feedback to pin 15. The PLL operation involves the division of the 14.4MHz
reference oscillator frequency by divider U710 and the internal divider of U701 down to a lower
frequency which corresponds to a sub-multiple of the radio channel spacing ie. 6.25kHz for
12.5/25kHz channel spacing or 5kHz for 20kHz channel spacing. The VCO frequency is
sampled and divided down to the same frequency after which it is phase compared to the
reference. Any error produces an offset to the Control Voltage output which is used to correct
the VCO frequency. A valid lock detect output is derived from pin 20 and is sampled by the
FPGA during transmit. If an unlocked signal is detected the radio will switch back to receive
mode.
3.3.3 VCO
The transmitter and receiver VCOs use low noise JFET transistors (Q600 RX, Q602 TX) and
inductors L602 (RX), L608 (TX) to generate the signals for the required band coverage.
Electronic tuning is provided by varactor diodes D600 to D608 with their control voltages derived
from the Loop Filter, PLL and Negative Bias Generator.
VCO selection and timing is controlled by the DSP via the RX and TX power supplies and
applied through switches Q601 (RX) and Q603 (TX). VCO buffer Q604/605 isolates the VCO
from load variations and active power supply filter Q615 minimises supply related noise. A PLL
feedback signal is sampled from the VCO buffer output via buffer Q607.
3.3.4 Negative Bias Generator and Loop Filter
A positive and negative varactor bias supply similar to the front-end varactor arrangement has
been used to achieve the required broadband tuning range of the VCOs. PLL device U701 is
programmed to deliver a fixed nominal +2.5V output from phase detector/charge pump CPPF or
CPP (selection depends on radio setup) regardless of the channel frequency selected. This
voltage is filtered to remove synthesiser noise and reference products by loop filter
C719/722/734 and R721/724/734. The resulting low noise voltage is applied to the cathode side
of the VCO varactor tuning diodes as a positive bias voltage. The negative bias supply
originates as a positive DC voltage (0.1V to 3.0V) at the DAC output of U701 (DOUT) with a
level relative to the programmed state of the radio (eg. channel frequency, TX/RX state). The
voltage is converted to a high level negative supply by VCO Varicap Negative Supply Q700 to
Q703. The -17V rail of this supply is generated by U300B/C with D304 to D307 providing the
voltage multiplying effect needed to achieve -17V. The output of the negative supply is applied
directly to the VCO varactor anodes as the negative tuning voltage VCAP BIAS.
3.3.5 Phase Modulator
The modulation path for audio, data and higher frequency CTCSS signals is via D609 and its
associated components in the TX VCO. The reference input to the PLL (FXTAL) provides the
low frequency modulation path in conjunction with phase modulator Q714 to Q716. U711A is a
low pass filter which provides 6dB per octave attenuation to frequencies above approximately
180Hz. Modulation balance adjustment is carried out using a CODEC generated 100Hz square
wave applied to TX MOD1. A DAC output from the Alignment Tool is applied to buffer U711B
and ramp generator Q711 to Q713 via the TUNE BAL line to adjust the low frequency
modulation level.
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