PAGE 28 TECHNICAL DESCRIPTION
32 PF1 on the DSP (U28) 3.3V Digital
33 I
2
C Data (SDA) 3.3V Digital
34 RX_FRAME signal for High Speed Serial Port 1 on the IXP
(U34)
3.3V Digital
35 Active-Low RING signal (indicating half-wave ringing detect
output signal) from PSTN interface (U7)
3.3V Digital
36 GPIO_IN6 Signal to CPLD (U22) 3.3V Digital
37 SPI_CS_DAC from IXP GPIO(10) 3.3V Digital
38 RX_FRAME signal for High Speed Serial Port 0 on the IXP
(U34)
3.3V Digital
39 TX_CLK signal for High Speed Serial Port 1 on the IXP (U34) 3.3V Digital
40 RX_DATA signal for High Speed Serial Port 0 on the IXP
(U34)
3.3V Digital
41 DSP Memory Select DSP_AMS3_N to CPLD (U22) 3.3V Digital
42 Spare I/O Pin CIO3 on CPLD (U22) 3.3V Digital
43 TDI JTAG Signal to CPLD (U22), connected to IXP GPIO(11) 3.3V Digital
44 TX_FRAME signal for High Speed Serial Port 0 on the IXP
(U34)
3.3V Digital
45 DSP_IRQA output from CPLD (U22) 3.3V Digital
46 GPIO_IN5 to CPLD (U22) 3.3V Digital
47 TMS JTAG Signal to CPLD (U22) 3.3V Digital
48 TX_DATA signal for High Speed Serial Port 0 on the IXP
(U34)
3.3V Digital
49 ENET0_INT_N to IXP GPIO(4) 3.3V Digital
50 Audio Output 1 from Codec C2 (U52) after passing through
the 1
st
Op-Amp stage
Audio Signal
51 DSP_IRQB output from CPLD (U22) 3.3V Digital
52 TCK JTAG Signal to CPLD (U22) 3.3V Digital
53 CPLDI_CS_N 3.3V Digital
54 DSP_IRQA output from CPLD (U22) 3.3V Digital
55 GPIO_IN3 to CPLD (U22) 3.3V Digital
56 GPIO_IN2 to CPLD (U22) 3.3V Digital
57 Audio Input 2 to Codec C2 (U52) prior to being converted
from single-ended to differential
Audio Signal
58 IXP Write Strobe IXP_WR_N 3.3V Digital
59 Active-Low Global Reset 3.3V Digital
60 Anti-Aliasing Filter Selector, generated by DSP PF11 3.3V Digital
61 SPI_MOSI generated by IXP GPIO12 3.3V Digital
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