Sony CDX-540RF - Page 36

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Pin No. Pin Name I/O Description
66 LOAD2 I
Save end detect switch (SW2) input terminal
“L”: When completion of the disc save operation
67 to 70 NC — Not used (open)
71 CH.F O
Motor drive signal (save direction) output to the chucking motor drive (IC201)
“L” active *1
72 CH.R O
Motor drive signal (chucking direction) output to the chucking motor drive (IC201)
“L” active *1
73 ELVR O
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
74 ELVF O
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *2
75 BUCHK I Battery detection signal input “H”: battery on
76 MGLK I Magazine detect switch (SW201) input terminal “L”: magazine is set
77 SQSO I Subcode Q/text serial data input from the CXD2598Q (IC101)
78 NC — Not used (open)
79 SQCK O Subcode Q/text serial data transfer clock signal output to the CXD2598Q (IC101)
80 KEYACK I
Input of acknowledge signal for the key entry
Acknowledge signal is input to accept from the remote commander in the power off status
81 NC — Not used (open)
82 SCOR I Subcode sync (S0+S1) detection signal input from the CXD2598Q (IC101)
83 SIRCS I SIRCS signal input from the remote commander
84 TEX I Sub system clock input terminal Not used (open)
85 TX O Sub system clock output terminal Not used (open)
86 VSS — Ground terminal
87 VDD — Power supply terminal (+5V)
88 NC — Not used (open)
89 LIMSW I
Sled limit in detect switch (SW3) input terminal
“L”: When the optical pick-up is inner position
90 FOK I Focus OK signal input from the CXD2598Q (IC101) “H” is input when focus is on (“L”: NG)
91 GFS I Guard frame sync signal input from the CXD2598Q (IC101) “L”: NG, “H”: OK
92 SCLK O Serial data transfer clock signal output to the CXD2598Q (IC101)
93 SENS I Internal status signal (sense signal) input from the CXD2598Q (IC101)
94 XRST O System reset signal output to the CXD2598Q (IC101) “L”: reset
95 ADON O Power supply on/off control signal output for the A/D converter “L”: power on
96 PLLCE O Chip enable signal output to the PLL IC (IC781)
97 PLLCLK O Serial data transfer clock signal output to the PLL IC (IC781)
98 PLLDATA O Serial data output to the PLL IC (IC781)
99, 100 NC — Not used (open)
*1 chucking motor (M103) control
STOP
LOAD
CHUCKING
SAVE BRAKE
CH.F (pin ua) “H”“H”“L”“L”
CH.R (pin us) “H”“L”“H”“L”
Mode
Terminal
*2 elevator motor (M104) control
STOP
ELEVATOR
UP
ELEVATOR
DOWN
BRAKE
ELVF (pin uf) “H”“L”“H”“L”
ELVR (pin ud) “H”“H”“L”“L”
Mode
Terminal