Sony HCD-CP505 - BD (MD) Board IC Block Diagrams

73
HCD-CP505
– BD (MD) Board –
IC401 BH6519FS-E2
IC101 CXA2523AR
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA– CAPA+ IN2R IN2F VM2 OUT2F PGND2 OUT2R VM12 OUT1R PGND1 OUT1F VM1 IN1F IN1R V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVEPREDRIVE
PREDRIVEPREDRIVE
AMP
INTERFACE
AMPAMPAMP
V
DD
PSB
AMP
–1
–2
+
–
IVR
BB
+
–
IVR
AA
+
–
IVR
CC
+
–
IVR
DD
+
–
IVR
+
–
EE
EE'
EFB TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36
BOTM
35
ABCD
34
FE
33
AUX
32
ADFG
31
ADAGC
30
ADIN
29
ADFM
28
SE
27
CSLED
26
TE
25
WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12
APCREF
11
APC
10
PD
9
F
8
E
7
D
6
C
5
B
4
A
3
VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+
–
–
+
AUXSW
COMMAND
+
–
IVR
GSW
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
–
–
–
–
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+ –
RFA1
–
–
–
–
1
2
–
–
–
1
2
GRVA
OFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC EQ
EQ
DET
P-P
WBL
3T
WBL
TEMP
PBH
–
+
USROP
+
–
USRC
3T
BPF3T
PEAK3T
1
I
2
J
RFA3
PBSW
AUX
SW
IV
ESW
EBAL