Sony HCD-DZ520K - Page 35

5252
HCD-DZ520K/DZ620K
HCD-DZ520K/DZ620K
• IC Block Diagrams
– MAIN Board –
IC2200 PCM1803DBR
VINL 1
VINR
2
VERF1
3
VERF2
4
VCC
5
AGND
6
PDWN 7
BYPAS
8
FSYNC
9
LRCK
10
MODE120
MODE0
19
FMT1
18
FMT0
17
OSR16
SCKI15
VDD
14
DGCD
13
DOUT
12
BCK
11
Single-End
/Differential
Converter
5 th Order
Delta-Sigma
Modulator
5 th Order
Delta-Sigma
Modulator
Reference
Single-End
/Differential
Converter
× 1/64 (× 1/128)
Decimation
Filter
with
DC Cut Filter
Power Supply
Clock and Timing Control
Serial
Interface
Mode/
Format
Control
IC3010, IC3020, IC3030 CXD9788AR
S P
Sampling Rate
Converter
DF1
DF2
Gain
Control
Filter
&
LOW
CUT
Filter
Serial Control
Liner
Interpolator
∆ ∑ Converter
XVSS
PWM
INIT/MUTE
Clock Generator
Clock Generator
(Secondary Clock System)
1
VSUBC
2
VSSR
VSSL
VSSL
VSSR
3
OUTR2
OUTL2
OUTR1
OUTL1
4
VDDR
DVDD
DVSS
VDDL
5
6
7
8
XOVSS
XOVDD
9
XFSOOUT
10 11
NSPMUTE
12
SOFTMUTE
13
PGMUTE
SCSHIFT
14
SCDT
15
SCLATCH
OVF FLAGR
OVF FLAGL
16
SFLAG
INIT
17
MCKSEL
18
LRCK
19
BCK
20
DATA
BFVDD
BFVSS
TEST
DVDD
XFSIIN
21
42
43
41
40
39
38 37
XFSOIN
36
XVDD
35
HPVDDL
34
HPOUTL2
33
HPVSSL
32
31
HPVDDR
30
HPOUTR1 HPOUTL1
29
28
HPVSSR
27
26
25
HPOUTR2
24
FSOI
23
FSOCKO
22
4445
46
47
48
(Primary Clock System)
IC3050 TK1118CSCL-G
1 2 3
5 4
VCONT
GND
NP
VIN VOUT
CONTROL
CIRCUIT
OVER HEAT &
OVER CURRENT
PROTECTION
BANDGAP
REFERENCE
IC3100, IC3150, IC3200, IC3250, IC3300, IC3400, IC3500 CXD9883M
1
10
9
8
11
12
13
14
7
6
15
16
17
18
3
4
5
20
19
2
AGND
GND
GND
PGND
PGND
PGND
PGND
PGND
PGND
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Stuck
Detect
Stuck
Detect
Timing
Control
Timing
Control
Protection
Logic
Protection
Logic
Gate
Drive
Gate
Drive
Gate
Drive
Gate
Drive
Over
Current
Fault
Over
Current
Fault
Over
Current
Fault
Over
Current
Fault
Programmable
Current
sense
OUT_B
OUT_B
OUT_B
PVDD_B
PVDD_B
PVDD_B
OUT_A
OUT_A
OUT_A
PVDD_A
PVDD_A
PVDD_A
REG
BST_B
GVDD_B
VDD
PWM_B
M1
M2
M3
VREG
OC_ADJ
PWM_A
/RESET
/SD
/OTW
GVDD_A
BST_A
Protection
and
Reset
Logic
OLP
OTP
CB3C
Temperature
waming/error
Power-Up
Reset
Under
Voltage
Protection
/HIZ_HS_B
/HIZ_HS_A
/HIZ_LS_B
/HIZ_LS_A
/OCL_B
/OCL_A
/OCH_B
/OCH_A
/RESET_A
/RESET_B
VREG
/HIZ_HS_X
/HIZ_LS_X
/OCH_X
/OCL_X
/RESET_X
/PCR
/UVP
/UVP
/UVP_VREG
VREG
GVDD_A
GVDD_B
VREG
w w w . x i a o y u 1 6 3 . c o m
Q Q
3
7
6 3
1 5 1 5
0 9 9
2
8 9
4 2
9 8
T E L 1 3 9 4 2 2 9 6 5 1 3 9 9 2 8 9 4 2 9 8 0 5 1 5 1 3 6 7 3
Q Q
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