Sony PMC-D305 - Page 46

1.3 ± 0.2 Vp-p
– 69 –
– 70 –
4.8 Vp-p
16.9344 MHz
4.8 Vp-p
240 ns
6.7 Vp-p
280 ns
5 Vp-p
22.6 µ s
Approx. 50 mVp-p
Approx. 50 mVp-p
36
PHD2 PHD1 PHD
33
LD
32
RF M
31
RF O
30
RF I
29
CP
28
CB
27
CC1
26
CC2
25
FOK
24 SENS
23 C. OUT
22 XRST
21 DATA
20 XLT
19 CLK
18 VCC
17 ISET
16 SL 0
15 SL M
14 SL P
13
12
TA O
TA M
11
FSET
10
TG2
9
TGU
8
SRCH
7
FE M
6
FE O
5
FLB
4
FGD
3
FDFCT
2
FEI
1
FEO
48VC
47TDFCT
46TZC
45ATSC
44TEI
43LPFI
42TEO
41VEE
40EI
39E
38F
37FE BIAS
+
+
–
+
+
–
+
–
+
–
+
–
+
–
+
–
+
+
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
–
+
+
–
–
+
+
–
+
–
+
–
+
–
+
–
APC
–
–
–
–
LEVELS
FOK
MIRR
DFCT
RF IV AMP2
RF IV AMP1
FE AMP
F IV AMP
E IV AMP
TE AMP
FZC COMP
BAL1 BAL2 BAL3
TOG1 TOG2 TOG3
TTL
IIL
IIL
TTL
TTL
IIL
• IIL DATA RESISTOR • INPUT SHIFT RESISTOR
• ADDRESS DECODER
• OUTPUT DECODER
HPF COMP LPF COMP
TZC COMP
DFCT
DFCT
TM1
FS4
ATSC
• WINDOW COMP
• FCS PHASE
COMPENSATION
• TRACKING
• PHASE
COMPENSATION
• ISET
FS1
FS2
TM4
TM5
TM6
TM3
TM7
TG2
• F SET
TG1
TM2
+
–
TOG1-3 FS1-4 TG1-2 TM1-7 PS1-4
BAL1-3
35 34
• Waveforms
– CD Section –
1 IC701 #¡ (RFO)
200 mV/DIV, 500 ns/DIV
2 IC701 $¢ (TI)
100 mV/DIV, 100 ns/DIV
3 IC701 2 (FI)
100 mV/DIV, 100 ns/DIV
4 IC702 @º (LRCK)
2 V/DIV, 10 µs/DIV
5 IC702 @™ (BCK)
2 V/DIV, 200 ns/DIV
6 IC702 @∞ (XPCK)
2 V/DIV, 200 ns/DIV
7 IC702 #∞ (XTAO)
2 V/DIV, 50 ns/DIV
• IC Block Diagrams
– CD Section –
IC701 CXA1782BQ
Note: This waveform is measured
between RFO and VC.