BIOS SETUP
36 MB720 User’s Manual
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Clock / Drive Control Press Enter ITEM HELP
AGP & P2P Bridge Control Press Enter Menu Level
CPU & PCI Bus Control Press Enter
Memory Hole Disabled
System BIOS Cacheable Enabled
Video RAM Cacheable Disabled
Init Display First PCI Slot
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Driver Control
Current FSB Frequency ITEM HELP
Current DRAM Frequency Menu Level
DRAM Clock By SPD
DRAM Timing Auto By SPD
DRAM CAS Latency 2.5
Bank Interleave Disabled
Precharge to Active (Trp) 4T
Active to Precharge (Tras) 9T
Active to CMD(Trcd) 3T
REF to ACT/REF to REF(Trfc 3T
ACT(0) to ACT(1) TRRD) 3T
DRAM Command Rate 2T Command
Phoenix - AwardBIOS CMOS Setup Utility
AGP & P2P Bridge Control
AGP Aperture Size 128M ITEM HELP
AGP Mode 8X
AGP Driving Control Auto Menu Level
AGP Driving Value DA
AGP Fast Write Enabled
AGP Master 1 WS Write Disabled
AGP Master 1 WS Read Disabled
AGP 3.0 Calibration cycle Disabled
VGA Share Memory Size 64M
Direct Frame Buffer Enabled
Select Display Device CRT
Panel Type 02
TV H/W Layout Default
HDTV Type HDTV 720P
TV Encoder Input Mode RGB Input
TV Type NTSC
TV Output AUTO Detect Disabled
TV Output Connector Press Enter
Anti-DotCrawl Disabled
Phoenix - AwardBIOS CMOS Setup Utility
CPU & PCI Bus Control
PCI Master 0 WS Write Enabled ITEM HELP
PCI Delay Transaction Enabled Menu Level
Vlink mode selection Mode 1 Menu Level
Vlink 8x Support Enabled
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