ST STM32H743 Series User Manual

Debug management AN4938
26/48 DocID029918 Rev 1
5 Debug management
5.1 Introduction
The host/target interface is the hardware equipment that connects the host to the application
board. This interface is made of three components: a hardware debug tool, a JTAG or SW
connector and a cable connecting the host to the debug tool.
Figure 16 shows the
connection of the host to the evaluation board.
Figure 16. Host to board connection
5.2 SWJ debug port (serial wire and JTAG)
The core of STM32H743/753xx devices integrates the Serial Wire / JTAG Debug Port (SWJ-
DP). It is an ARM
®
standard CoreSight debug port that combines a 5-pin JTAG-DP interface
and a 2-pin SW-DP interface.
• The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
• The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
For more details on the SWJ debug port refer to RM0433 SWJ debug port section (serial
wire and JTAG).
5.2.1 TPIU trace port
The TPIU trace port comprises four data outputs plus one clock output. The number of data
outputs can be configured by software and unused signals can be reused as GPIOs. If the
trace port is not required, all the signals can be used as GPIOs. By default, the trace port is
disabled.
The trace data and clock can operate at up to 133 MHz. As a result, care must be taken with
the layout of these signals: the trace connector should be located as close as possible to the
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ST STM32H743 Series Specifications

General

Core	ARM Cortex-M7
Flash Memory	Up to 2 MB
SRAM	Up to 1 MB
ADC	Up to 3x 16-bit
DAC	Up to 2x 12-bit
Communication Interfaces	USB, CAN, SPI, I2C, UART, Ethernet
Operating Temperature	-40°C to 85°C
Package	BGA, LQFP

Summary

Introduction to STM32H7x3 Hardware Development

Hardware Features Overview

1 Power Supplies

1.2 Power supply scheme

1.3 Reset and power supply supervisor

Covers POR/PDR, PVD, AVD, and system reset mechanisms.

3 Clocks

3.1 HSE oscillator clock

Details on HSE clock sources: external user clock and crystal resonator.

3.2 LSE oscillator clock

Information on LSE clock sources: external user clock and crystal resonator.

3.3 Clock security system (CSS)

Explains the CSS for HSE and LSE oscillators to ensure clock stability.

4 Boot Configuration

4.1 Boot mode selection

How to select boot modes using BOOT pin and option bytes.

4.3 System bootloader mode

5 Debug Management

5.2 SWJ debug port (serial wire and JTAG)

Overview of the SWJ-DP, combining JTAG and SW-DP interfaces.

5.3 Pinout and debug port pins