DocID023833 Rev 5 27/36
STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations
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2.10 ADC peripheral limitations
2.10.1 ADC sequencer modification during conversion
Description
If an ADC conversion is started by software (writing the SWSTART bit), and if the
ADC_SQRx or ADC_JSQRx registers are modified during the conversion, the current
conversion is reset and the ADC does not restart a new conversion sequence automatically.
If an ADC conversion is started by hardware trigger, this limitation does not apply. The ADC
restarts a new conversion sequence automatically.
Workaround
When an ADC conversion sequence is started by software, a new conversion sequence can
be restarted only by setting the SWSTART bit in the ADC_CR2 register.
2.11 DAC peripheral limitations
2.11.1 DMA underrun flag management
Description
If the DMA is not fast enough to input the next digital data to the DAC, as a consequence,
the same digital data is converted twice. In these conditions, the DMAUDR flag is set, which
usually leads to disable the DMA data transfers. This is not the case: the DMA is not
disabled by DMAUDR=1, and it keeps servicing the DAC.
Workaround
To disable the DAC DMA stream, reset the EN bit (corresponding to the DAC DMA stream)
in the DMA_SxCR register.
2.11.2 DMA request not automatically cleared by DMAEN=0
Description
if the application wants to stop the current DMA-to-DAC transfer, the DMA request is not
automatically cleared by DMAEN=0, or by DACEN=0.
If the application stops the DAC operation while the DMA request is high, the DMA request
will be pending while the DAC is reinitialized and restarted; with the risk that a spurious
unwanted DMA request is serviced as soon as the DAC is re-enabled.
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