STMicroelectronics STM32F427 User Manual

DocID023833 Rev 5 11/36
STM32F42xx and STM32F43xx STM32F42xx and STM32F43xx silicon limitations
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2.1.3 Wakeup sequence from Standby mode when using more than
one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which
generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode
entry, otherwise the MCU wakes up immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by
setting the CWUF bit), it may mask further wakeup events on the input of the edge detector.
As a consequence, the MCU might not be able to wake up from Standby mode.
Workaround
To avoid this problem, the following sequence should be applied before entering
Standby mode:
• Disable all used wakeup sources,
• Clear all related wakeup flags,
• Re-enable all used wakeup sources,
• Enter Standby mode
Note: Be aware that, when applying this workaround, if one of the wakeup sources is still kept
high, the MCU enters Standby mode but then it wakes up immediately generating a power
reset.
2.1.4 Full JTAG configuration without NJTRST pin cannot be used
Description
When using the JTAG debug port in debug mode, the connection with the debugger is lost if
the NJTRST pin (PB4) is used as a GPIO. Only the 4-wire JTAG port configuration is
impacted.
Workaround
Use the SWD debug port instead of the full 4-wire JTAG port.

STMicroelectronics STM32F427 Specifications

General

Series	STM32F4
Core	ARM Cortex-M4
Max Clock Speed	180 MHz
ADC Channels	Up to 24
ADC Resolution	12-bit
DAC Channels	2
DAC Resolution	12-bit
Timers	17
Communication Interfaces	I2C, SPI, UART, USB, CAN
Operating Voltage	1.8 V to 3.6 V
Operating Temperature	-40°C to 85°C
Package	LQFP100

Summary

ARM 32-bit Cortex-M4 with FPU Limitations

Cortex-M4 Interrupted Loads to Stack Pointer Can Cause Erroneous Behavior

Interrupt during SP load causes erroneous behavior and extra execution of the load instruction.

STM32F42xx and STM32F43xx Silicon Limitations

System Limitations

Limitations related to general system operations, clocking, and debugging modes.

IWDG Peripheral Limitation

Specific limitation concerning the Independent Watchdog Timer (IWDG) in STOP mode.

I2C Peripheral Limitations

Issues found with the Inter-Integrated Circuit (I2C) peripheral functionality.

USART Peripheral Limitations

Problems identified with the Universal Synchronous/Asynchronous Receiver/Transmitter (USART) peripheral.

OTG_FS Peripheral Limitations

Limitations concerning the On-The-Go Full Speed (OTG_FS) peripheral.

Ethernet Peripheral Limitations

Issues related to the Ethernet controller and its functionality.

FMC Peripheral Limitation

Limitations found in the Flexible Memory Controller (FMC) operations.

SDIO Peripheral Limitations

Specific issues with the Secure Digital Input/Output (SDIO) interface.

ADC Peripheral Limitations

Limitations impacting the Analog-to-Digital Converter (ADC) functionality.

DAC Peripheral Limitations

Problems affecting the Digital-to-Analog Converter (DAC) operations.

Revision Code on Device Marking

TFBGA216 Top Package View

Shows the marking composition for the TFBGA216 package, including revision code.

WLCSP143 Top Package View

Illustrates the marking layout for the WLCSP143 package with revision code.

LQFP208 Top Package View

Details the marking structure of the LQFP208 package, including revision code.

UFBGA176 Top Package View

Shows the marking composition for the UFBGA176 package, highlighting the revision code.

LQFP176 Top Package View

Depicts the marking layout for the LQFP176 package, indicating revision code placement.

LQFP144 Top Package View

Presents the marking scheme for the LQFP144 package, showing the revision code field.

LQFP100 Top Package View

Illustrates the marking composition for the LQFP100 package, including the revision code.

Revision History

Document Revision History

Lists changes made to the document across different revisions.