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Series | STM32F4 |
---|---|
Core | ARM Cortex-M4 |
Max Clock Speed | 180 MHz |
ADC Channels | Up to 24 |
ADC Resolution | 12-bit |
DAC Channels | 2 |
DAC Resolution | 12-bit |
Timers | 17 |
Communication Interfaces | I2C, SPI, UART, USB, CAN |
Operating Voltage | 1.8 V to 3.6 V |
Operating Temperature | -40°C to 85°C |
Package | LQFP100 |
Interrupt during SP load causes erroneous behavior and extra execution of the load instruction.
Limitations related to general system operations, clocking, and debugging modes.
Specific limitation concerning the Independent Watchdog Timer (IWDG) in STOP mode.
Issues found with the Inter-Integrated Circuit (I2C) peripheral functionality.
Problems identified with the Universal Synchronous/Asynchronous Receiver/Transmitter (USART) peripheral.
Limitations concerning the On-The-Go Full Speed (OTG_FS) peripheral.
Issues related to the Ethernet controller and its functionality.
Limitations found in the Flexible Memory Controller (FMC) operations.
Specific issues with the Secure Digital Input/Output (SDIO) interface.
Limitations impacting the Analog-to-Digital Converter (ADC) functionality.
Problems affecting the Digital-to-Analog Converter (DAC) operations.
Shows the marking composition for the TFBGA216 package, including revision code.
Illustrates the marking layout for the WLCSP143 package with revision code.
Details the marking structure of the LQFP208 package, including revision code.
Shows the marking composition for the UFBGA176 package, highlighting the revision code.
Depicts the marking layout for the LQFP176 package, indicating revision code placement.
Presents the marking scheme for the LQFP144 package, showing the revision code field.
Illustrates the marking composition for the LQFP100 package, including the revision code.
Lists changes made to the document across different revisions.