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DocID023833 Rev 5 3/36

STM32F42xx and STM32F43xx Contents

2.5.5 nRTS signal abnormally driven low after a protocol violation . . . . . . . . 17

2.6 OTG_FS peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.1 Data in RxFIFO is overwritten when all channels are disabled

simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.6.2 OTG host blocks the receive channel when receiving IN packets and no

TxFIFO is configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.3 Host channel-halted interrupt not generated when the channel is

disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6.4 Error in software-read OTG_FS_DCFG register values . . . . . . . . . . . . 18

2.7 Ethernet peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.1 Incorrect layer 3 (L3) checksum is inserted in transmitted IPv6 packets

without TCP, UDP or ICMP payloads . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.2 The Ethernet MAC processes invalid extension headers in the received

IPv6 frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7.3 MAC stuck in the Idle state on receiving the TxFIFO flush command

exactly 1 clock cycle after a transmission completes . . . . . . . . . . . . . . . 19

2.7.4 Transmit frame data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.7.5 Successive write operations to the same register might not be fully

taken into account . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8 FMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.8.1 Dummy read cycles inserted when reading synchronous memories . . . 23

2.8.2 FMC synchronous mode and NWAIT signal disabled . . . . . . . . . . . . . . 23

2.8.3 Read access to a non-initialized FMC_SDRAM bank . . . . . . . . . . . . . . 23

2.8.4 Corruption of data read from the FMC . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.8.5 Interruption of CPU read burst access to an end of SDRAM row . . . . . 24

2.8.6 FMC NOR/PSRAM controller: asynchronous read access on bank 2 to 4

returns wrong data when bank 1 is in synchronous mode

(BURSTEN bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.8.7 FMC dynamic and static banks switching . . . . . . . . . . . . . . . . . . . . . . . 25

2.9 SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9.1 SDIO HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.9.2 Wrong CCRCFAIL status after a response without CRC is received . . . 25

2.9.3 Data corruption in SDIO clock dephasing (NEGEDGE) mode . . . . . . . . 26

2.9.4 CE-ATA multiple write command and card busy signal management . . 26

2.9.5 No underrun detection with wrong data transmission . . . . . . . . . . . . . . 26

2.10 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.10.1 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 27

2.11 DAC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.11.1 DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

STMicroelectronics STM32F427 User Manual

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