Supermicro X12SPW-TF - Page 76

Super X12SPW-TF/F User's Manual
76
CPU Conguration
The following CPU information is displayed:
• Processor BSP Revision
• Processor Socket
• Processor ID
• Processor Frequency
• Processor Max Ratio
• Processor Min Ratio
• Microcode Revision
• L1 Cache RAM (Per Core)
• L2 Cache RAM (Per Core)
• L3 Cache RAM (Per Package)
• Processor 0 Version
CPU1 Core Disable Bitmap
CPU1 Core Disable Bitmap
Core Disable Bitmap(Hex)
Select 0 to enable all cores or FFFFFFFFFFF to disable all cores. One core must be
enabled.
Hyper-Threading (ALL)
Select Enable to support Intel Hyper-hreading Technology to enhance CPU performance. The
options are Disable and Enable.
Hardware Prefetcher
If set to Enable, the hardware prefetcher prefetcesh streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Enable
and Disable.
Adjacent Cache Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Enable and Disable.