Supermicro X12SPW-TF - Page 84

Super X12SPW-TF/F User's Manual
84
Data Scrambling for DDR4
Use this feature to enable or disable data scrambling for DDR4 memory. The options
are Disable and Enable.
2x Refresh Enable
Use this feature to enable 2x memory refresh support to enhance memory performance.
The options are Auto, Disable, and Enable.
Memory Topology
This feature displays the information of memory modules detected by the BIOS.
Memory RAS Conguration Setup
Enabled Pcode WA for SAI PG
Use this feature to enable Pcode Work Around for SAI Policy group for A Step. The
options are Disabled and Enabled.
Mirror Mode
This feature allows memory to be mirrored between two channels, providing 100%
redundancy. The options are Disable, Full Mirror Mode, and Partial Mirror Mode.
UEFI ARM Mirror
This feature allows the system to imitate the bahavior of the UEFI based Address
Range Mirror with setup option. The options are Disabled and Enabled.
Correctable Error Threshold
Use this feature to specify the threshold value for correctable memory-error logging,
which sets a limit on the maximum number of events that can be logged in the memory
error log at a given time. The default setting is 512.
Partial Cache Line Sparing PCLS
Use this feature to enable or disable Partial Cache Line Sparing (PCLS). The options
are Disabled and Enabled.
ADDDC Sparing
Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede-
termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disabled and Enabled.