Technics SL-HD550

To MAIN CIRCUIT(CN402)
on SCHEMATICDIAGRAM-4
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2122232425262728293031323334353637383940
BCLK
LRCK
SRDATA
DVDD1
DVss1
TX
MCLK
MDATA
MLD
SENSE
/FLOCK
/TLOCK
BLKCK
SQCK
SUBQ
DMUTE
STAT
/RST
SMCK
CSEL
TRV TVD PC ECM ECS KICK TRD FOD
VREF
FBAL TBAL FE TE RFENV VDET OFT TRCRS /RFDET BDO LDON
PLLF2
DSLF2
WVEL
ARF
IREF
DRF
DSLF
PLLF
VCOF
AV
DD2
AVss2
EFM
PCK
VCOF2
SUBC
SBCK
Vss
X1 IN
X2 OUT
V
DD
BYTCK
/CLDCK
FCLK
IPFLAG
FLAG
CLVS
CRC
DEMPH
RESY
IOSEL
/TEST
AV
DD1
OUTL
AVss1
OUTR
RSEL
IOVDD
PSEL
MSEL
SSEL
2321 2220191817161514
1
32 4 5 6 7 8 9 10 11 12 13
TP15 TP19 TP22
A
B
TP23
TP21
C727
50V1
C728
50V1
C725
1000P
C726
1000P
R718
1K
R717
1K
C754
470P
C730
0.1
C731
10V220
R721
100
C732
10V220
C733
0.1
C753
470P
A
B
CN702
C743
0.1
TP17
L701
AB
TP14TP13
C
TP12TP8TP7TP6
TP4
TP3
DGHIJK
TP1
S701
(REST)
TP16
C745
0.1
A
B
C
D
G
H
I
J
K
GEDCBAABC EFGHI
Q702
DTC143XUA106
SWITCHING
R712
220
C718
0.1
C717
0.1
C744
8200P
R709
68K
R711
82K
C722
3P
X701
(33.8688MHz)
R714
6.8K
C721
3P
C724
0.1
C723
10V220
IC702
MN662790RSC
SERVO PROCESSOR/
DIGITAL SIGNAL PROCESSOR/
DIGITAL FILTER/
D/A CONVERTER
+B(2)
Rch OUT
C
5V
SUBC
/RST
STAT
SBCK
SUBQ SQCK
BLKCK
SPEED
MLD
MDATA
MCLK
P.GND
+B(1)
TX
CLDCK
D.GND
A.GND
Lch OUT
REST SW
L702
D
TP2
R753
10
F
R741
47K
R742
220K
C760
0.1
NC
NC
TP20
SCHEMATIC DIAGRAM-2
TP5
7.9V
3.3V
3.3V
3.3V
3.3V
1.7V
(0.2V)0V
3.3V
0V
3.3V
3.3V (3V)
0V (3.3V)
3.3V
1.7V
3.3V(0V)
1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V 1.7V
3.3V(0V)
0V(3.3V)
0V 0V
1.7V
1V
(1.2V)
1.7V
0V
3.3V
1.6V
1.6V
3.3V
3.3V
3V 1.5V
3.3V
1.5V 3.3V
3.3V
PLAY
1kHz, 0dB
2.4V
P-P
PLAY
0V
3.3V
T 13.3ms.
400mV
P-P
F=33.8688MHz
1.9V
P-P
F=33.8688MHz
PLAY
2ms. 0.1V/DIV.
0.4V
P-P
PLAY
0.2V
P-P
2ms. 0.1V/DIV.
PLAY
0V
3.3V
0.1us. 2V/DIV.
PLAY
0V
3.3V
T 13.3ms.
3.3V
0V
3.3V
3.3V
3.3V
1.7V
1.7V
:POSITIVE VOLTAGE LINE :CD SIGNAL LINE
PLAY
0.7V
P-P
0.5us. 0.2V/DIV.
PLAY
0V
3.3V
F=75Hz
(3.1V)
(3V)
PLAY
0V
3.3V
T 13.3ms.