Technics SL-PG200A

* 1C301 (MN6626): Digi
Division
tal signal processor
Function
GND terminal
Reference current input
RF signal input
DSL bias terminal
(Not used, open)
DSL loop filter terminal
PLL loop filter terminal
Power supply terminal
RF signal polarity setting
terminal
(Not used, connected to VDD)
Test terminal
Flag terminal
SL-PG200A
Function
Sub-code block clock (f=75Hz)
De-emphasis ON signal
(“H": ON)
Emphasis signal
Command load signal
(“L”: LOAD)
Command clock signal
Command data signal
Muting input (“H”: MUTE)
System clock (f=4.2336 MHz)
Status signal
(CRC, CUE, CLVS, TTSTOP,
FCLV, SQOK)
Sub-code CRC check terminal
(“H”: OK, “L”: NG)
Interpolation flag terminal
Crystal frame clock
(Not used, open)
aap
fel [o|
eee
SRDATA
Byte clock (Not used, open)
Word clock (Not used, open)
Reset terminal
Digital audio signal
(Not used, open)
Lch deglitch signal
(Not used, open)
Rch deglitch signal
(Not used, open)
Serial data output (MSB first)
SCK
Serial bit clock output
LRCK L/R discriminating signal
XCK
Crystal OSC terminal
(f= 16.9344 MHz)
Frequency division clock signal
(Not oe open)
(f= ae x CK=88.2kHz)
Test terminal
(Connected to GND)
Crystal OSC terminal
(f =16.9344 MHz)
GND terminal
Sub-code Q data
Sub-code Q register clock
Sub-code frame clock
(f=7.35kHz) (Not used, open)
Sub-code serial output data
(Not used, open)
Sub-code serial output clock
(Not used, open)
Tracking servo ON signal
Turntable servo phase synchro
signal
(“H”: CLV, “L”: Rough servo)
Turntable motor ON signal
(“L”: ON)
Turntable motor drive signal
(Forced mode)
Turntable motor drive signal
(Servo error signal)
Power supply terminal
Test terminal (Normal: “H”)
“SUBQ” terminal mode select
(“H”: Q code buffer)
“SMCK” terminal frequency
select (“L”: SMCK= 4.2336 MHz)
Re-synchronizing signal of frame
sync. (Not used, open)
Drop-out detection signal
(“H”: Drop-out)
(Not used, connected to GND)
EFM signal (Not used, open)
PLL extract clock (f= 4.3218 MHz)
Phase comparated signal of
EFM and PCK (Not used, open)