Circuit Description—485/R485 Service
The network connected between U650 and U660 is the
bandwidth limiter network. The network provides a con
stant impedance of 50 Cl per side at all frequencies looking
from pins 4 and 10 of U660. In the full bandwidth mode,
signal from pins 5 and 9 of U650 loops through U660 and
is terminated in the bandwidth limit network. In the
20 MHz mode, the signal is obtained from pins 6 and 8 of
U650. In passing through the bandwidth limit network
signals above 20 MHz are attenuated at 12 dB/octave.
U660 is an FT doubler configuration with the input
T coil peaked. Bias for the inner set of bases is set by R672
and R673. The output transistors are high voltage devices
which drive the CRT's distributed deflection structure.
In the event of a loss of a CRT termination resistor, the
long tail current through R657 pulls pins 2, 8, and 3 of
U660 down. When the +27 V supply goes below 25 V,
Q686 turns on, turning on Q688 which shorts the 25 V
supply. The loss of the +25 V supply will shut down the
power supply inverter. See inverter current limiting.
SCALE FACTOR READOUT
Scale factor readout control circuitry is in U80. With a
IX probe or with an non-readout coded connector con
nected to the input connector code ring surrounding J1, pin
11 of U80 is connected to +5 V through R81. The voltage
at pin 11 is sensed by U80 and pin 10 is pulled down,
lighting the XI light emitting diode (LED), CR99. 11 kS2 to
ground from the code ring shuts off CR99, and turns on
CR98, the X10 LED. A 6.8 kf2 from the code ring to
ground will shut off the X I0 LED and light CR97, the
X100 LED. A short circuit on the code ring provides trace
ID which pulls down pin 7 of U80, shifts the trace upward
one-fourth of a division, and shuts off the scale factor light.
The trace ID signal goes to R289 on CH 1 and R389 on
CH 2 to provide trace shift in the vertical pre-amplifiers.
VERTICAL MODE CONTROL
U1535B controls the vertical logic (diagram 3) via two
control leads from pins 8 and 9. These leads also are
connected via Q1590 and Q1594 to the trigger logic
(diagram 4) when the trigger is NORM. The trigger logic is
independent of U1535B when CH 1 or CH 2 triggers are
called up.
U1535B is controlled by the mode switch in CH 1,
CH 2, ADD, or X-Y. In the ALT or CHOP mode, the IC's
control the input to pin 7 of U15358 to cause it to either
alternate on command from A GATE or to CHOP. When
the HORIZ is in ALT, and the vertical in ALT, U1535B
changes state only every other A GATE. Note that A GATE
is the signal that activates U1535 in ALT and the signal
from U1530B pin 6 only allows every other A GATE
through. U1535A output is A GATE 2, and U1535B is A
GATE 4.
In the CHOP mode, U1585 is on and U1535B changes
state every time U1585 makes an output. While U1585 is
making an output a signal from U1585 pin 4 blanks to
prevent displaying the switching from CH 1 and CH 2 and
back.
Z AXIS
U1560 output drives the Z AXIS amplifier. U1560 is
controlled by the A and B GATES, the A-B control via pin
15, the INTENsity controls and the EXT Z AXIS.
The circuit consisting of Q1566 and Q1568 disconnects
the B INTENSITY control during X-Y or when A=1, 2, or
5 ns.
A TRIGGER AMPLIFIER
The Source Switch SW700 selects one of the four modes
which the 485 will trigger on: INT, LINE, EXT, or EXT +
10. Signals above approximately 1 MHz, except in HF REJ
are coupled through C705. R705 and R709 form a 1 Mf2
input resistance and a loss pad to compensate for the loss
across C705, matching high frequency and low frequency
gains. R708 protects Q712A input by limiting current when
CR711 or Q712A is forward biased. Q712A and Q712B
form a source follower with the source voltage very close to
zero. The source follower drives Q716, an emitter follower,
which drives U730. The balun coil T719 produces a
differential signal. U730, U738, and U740 are cascode
amplifiers. The slope switch SW720, switches the collectors
of U740 to give selection of the triggering slope.
A EXT TRIGGER IDENTIFY
The A EXT TRIG IDENTIFY function is driven by the
emitters of U730; this allows U830 to be coupled to the
trigger signal and the level control. The center line crossing
point of the A EXT TRIG signal corresponds to the trigger
point of the sweep for timing information.
When the EXT TRIGGER IDENTIFY switch is pushed,
U830 is turned on and its collectors are connected to the
vertical delay line via relay K410. VR838 and VR839
provide DC level shift.
The cables between J842 and J843 and relay K10 have a
time delay so that the EXT trigger signal will be displayed
with the same time position as signals arriving through CH 1
or CH 2 input.
3-3
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