Theory of Operation—492/492P Service Vol. 1 (SN B030000 & up)
fast retrace occurs. This retrace, unlike that following the A
memory display (cursor), is not required to be seen and is
thus blanked. This is accomplished by blanking control flip-
flop U1014B, which is controlled by the most significant bit
of the memory address and the display enable signal during
a marker cycle.
Memories. Integrated circuits U1026 and U2026 provide
8 k bits of random access memory for storage of the 1024
data points used in the digital storage system. Addressing is
controlled by address tristate buffers U1022 and U1016 dur
ing display of memory data and by horizontal control IC
U2032 during memory update.
The shaped signal is then applied through preamplifier
U2060 to the Deflection Amplifier circuits. The feedback
path around U2060 includes Horiz Gain adjustment R1055
to calibrate the amount of compensation required for deflec
tion sensitivity.
The horizontal deflection amplifier consists of two similar
circuits, one for each horizontal deflection plate. One circuit
is an inverting amplifier, the other operates in-phase. Inputs
to the inverting side are through the parallel combination of
resistors R3049, R3048, and capacitor C4057 to Q4038A.
High-frequency response compensation is provided by the
series connection of resistor R3048 and variable capacitor
C4057. High-frequency feedback is controlled by capacitor
C3043.
DEFLECTION AMPLIFIERS <^>
Refer to the block diagram adjacent to Diagram 26. The
Deflection Amplifier selects from among several inputs to
generate the drive signals for the crt plates, and generate a
signal to drive the auto-focus portion of the Z-Axis circuit.
Input signals are from the Horizontal Sweep, Readout, Vid
eo Filter, and Digital Storage circuits.
Horizontal Section
Signal lines HORIZ SIG (from the Digital Storage circuits)
and SWEEP (from the Sweep circuit), through edge connec
tor pins 49 and 51, are applied to switch IC U7055. One half
of U7055, under control of the STORAGE OFF signal from
the Digital Storage circuits, selects either HORIZ SIG or
SWEEP inputs. When the STORAGE OFF line is floating or
pulled high, the SWEEP signal is selected; when the line is
pulled low, the HORIZ SIG signal is selected. The selected
signal is then divided down from 1 V/div to 0.5 V/div by re
sistive divider R7051 and R7081 and buffered by U7073.
From buffer U7073, a sample of the signal is applied to a
rear panel connector via edge connector pin 48. The signal
is also applied to the other section of switch U7055 along
with the HORIZ R/O signal from the Readout circuits. Selec
tion between these two signals is controlled by the R/O OFF
signal, also from the Readout circuits, through edge connec
tor pin 3. When R/O OFF is floating or pulled high, the signal
from buffer U7073 is transmitted through the switch; when
the line is pulled low, the HORIZ R/O signal is selected.
From U7055, the signal is applied to a shaper network to
compensate for non-linearity in the crt deflection character
istics. This network consists of resistors R3051, R3052,
R4059, R4058, R4057, R4062, R4061, and R3059, plus di
odes CR4052, CR4051, CR4058, and CR3058. Note that
HORIZ POS voltage from the front panel via edge connector
pin 47 through resistor R2053 is applied to the shaper cir
cuit so the shape correction factor relates to the crt
deflection.
Input to the non-inverting side is through resistor R5029
to the base of Q4025A. R3019 and R5035 set the dc level
for the feedback loop to the base of Q4025B. Variable ca
pacitor C5021 provides adjustment to set transient gain.
Again, high frequency feedback is controlled by capacitor
C2021.
Gain of each amplifier section is approximately 20. (Hori
zontal deflection sensitivity of the crt is approximately
21.3 V/div per side.) Each section is single-ended and incor
porates at the input side, a gain-degenerated dual (for tem
perature compensation) PNP transistor connected as a
differential amplifier. For example, Q4038B of the right de
flection amplifier drives emitter follower Q4047.
Signals with a low rate of change drive the output tran
sistor through R5037, P3033. As the rate of rise increases,
the drop across R5037 increases and when it reaches
0.6 V, either Q4035 or Q4042 are biased on. These transis
tors provide the high current drive for the output transistors.
When the signal rate of change is low, Q1043 drives the crt
deflection plate and Q1049 provides bias current for the am
plifier. As the rate of rise increases, C3039 couples signal to
the base of Q1049. Q1049 provides the positive drive to the
deflection plate, Q1043 the negative drive. Each output tran
sistor can provide a 200 V excursion in about 1 με.
The horizontal amplifiers operate with approximately
1 mA of bias current in the output stage, as set by the cur
rent through resistor R3031 and the resistors connected at
the base and emitter of output transistor Q1049. The cur
rent through resistor R3031 also provides the operating cur
rent for the dual input stage (Q4038A and B). Emitter
follower Q4047 operates at approximately 2.5 mA. The out
put stage is degenerated for fast steps by emitter resistors
R1045 and R1034. For a 0V input, the output operating
level is set by current from the -1 5 V source through resis
tor R4033. Dc feedback resistor R3045 sets this output lev
el at approximately 142 V.
REV FEB 1983 5-45
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