Theory of Operation—492/492Ρ Service Vol. 1 (SN B030000 & up)
part of the input circuit of a feedback amplifier containing
U2043, Q3047, and driver transistor Q352. The feedback
n
path through R3040 and R2042 sets the voltage across a
four-terminal resistor R1040. This voltage in turn sets the
current of the resistor which is also emitter current for driver
transistor Q352. The oscillator coil current 1st LO Sense
adjustment R1031 sets the voltage gain of the amplifier
which changes the current drive to the oscillator coil.
Capacitor C3038 filters noise on the tune volts and volt
age reference inputs. Because of its effect on tuning speed,
the capacitor is in the circuit only in the phase-locked mode
with phaselock switched off, or when the phaselock option
is not included in the instrument. Normally Q5 of U4017 is
low, which through U3014B, causes Q3042 to cut off.
Reference Supply. Operational amplifier U2052 and sur
rounding circuitry form the — 10 V reference supply. One
side of preamplifier Q2052, biased by R1055 and VR1051,
sets a reference voltage at the inverting input of U2052. The
output voltage is set by R1034, the -10 V adjustment.
U2052 senses changes in load that are amplified by Q2052,
and changes the current through regulator transistor
Q2051. The diode network across the base-emitter junction,
limits the collector current to about 23 mA, protecting the
transistor from damage.
Mixer Bias Driver. The mixer bias driver circuit, which
consists of quad FET switch U1016, amplifier U1025A, and
buffer Q2025/Q1028, plus associated circuitry, furnishes the
required bias current (up to 20 mA) to the 1 st Mixer circuit.
The bias voltage varies from +1 V to — 1 V for the internal
mixer, and from +1 V to —2.25 V for an external mixer.
Regulator U1013/U1018, provides regulated +12 V and
-12 V across the three bias adjustment potentiometers,
R1013, R1026, and R1022. The voltage at the center arm of
one of thse potentiometers, or the output of U2018, (which
represents the front panel PEAKING control setting or
programmable bias) is selected by quad FET switch U1016
and applied to the input of U1025A. Quad FET U1016 is
controlled by Q1 through Q4 lines from data latch Q4017. A
low at any one of these outputs causes the associated FET
to conduct and connect that line to the input of U1025A.
U1025A drives a pair of transistors, Q1028/Q2025, con
nected as a complementary pair to provide the 1st Mixer
bias voltage.
Programmable Bias. When the microcomputer sends
address 7E to decoder U4034, pin 7 (output Y7) goes low.
At the end of data output cycle, data is clocked into either
U4024 or U4022, depending on which latch is enabled by
DB6 or DB7. This data is then converted to an analog cur-
U
rent by U3022 which is the current source for operational
amplifier U2018. The output of U2018 is a bias voltage that
REV AUG 1981
is fed to either the Preselector Driver board where it is
summed with the drive voltage for the Preselector; or, it is
fed through U1016/U1025A, and Q1025/Q2025 to the
829 MHz Diplexer, then through RF circuitry to the 1st Mix
er or external mixer port.
Oscillator Collector Supply. This circuit comprises am
plifier U4055, buffer Q3049, and surrounding circuitry.
U4055 holds Q3049 in saturation, so the collector of the
transistor remains at a fraction of a volt below +15 V. This
voltage is applied to the 1 st LO circuits.
PRESELECTOR DRIVER
The Preselector circuit, part of Option 01, provides input
selectivity that reduces spurious responses between 1.7
and 21 GHz. Refer to the block diagram adjacent to Dia
gram 37. The Preselector Driver furnishes the drive current
that operates the Preselector Coil, depicted on Diagram 12.
It also furnishes a voltage proportional to frequency through
the rear-panel ACCESSORIES connector for an external
unit. The circuit also drives the relay that selects the
preselector or low-pass filter. The Preselector Driver con
sists of the following major circuits:
1) the digital control circuit, which stores and decodes the
data from the microcomputer and control the other parts of
the Preselector Driver. The digital control circuit applies the
SPAN VOLTS signal to the oscillator voltage processor
when FM coil spans are selected; select the gain of the
oscillator voltage processor; turn off the drive signal to the
current driver for degauss cycles or when the preselector is
not in use; select the IF offset voltages to be combined with
the FINE TUNE VOLTS signal; add noise filtering at the
driver output when the preselector is not being swept; and
control the filter select switch;
2 ) the oscillator voltage processor, which attenuates and
offsets the input signal for application to the summing
amplifier;
3) the IF Offset stage, which applies an offset voltage to the
summing amplifier that is proportional to the IF frequency in
use, and to the fine tuning frequency changes of the 2 nd
Local Oscillator;
4) the summing amplifier, which combines the effective os
cillator frequency voltage and the IF Offset voltage, and
drives the tracking adjustment circuits;
5) the tracking adjustment circuit, which compensates for
different preselector sensitivities, compensates for IF offset
and any preselector offset, and compensates for non-linear
operation caused by magnetic saturation of the Preselector;
6 ) the final driver stage, which changes the applied voltage
signal into a current drive signal for the preselector coil;
7) the preselector switch driver, which drives the filter select
switch, depicted on Diagram 12. The switch requires a posi
tive pulse to select the lowpass filter and a negative pulse to
select the Preselector.
5-63
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