Ten-Tec JUPITER - Page 82

of U7 оп the CPU section (Figure 4-13) of
the Logic board. Тһе AUDIO- and
AUDIO+ signals are the balanced output.
They exit the board via JP7 to the 81887
Keypad board. 02 and Ulla are audio
amplifiers that provide the AUX AUD .
OUT path to the REAR CONNECTORS
board ма Jil and Cable 10.
MIC AUDIO comes from the Keyboard
Board via Cable 6 and J3. U13a and U13b
provide amplification of the signal and
R72 provides an internal control for
setting the range of the operator's MIC
control on the front panel. From U13a the
amplified signal goes to an input of the
codec IC, U19.
The codec section of the Logic schematic,
Figure 4-12, is the bridge between
JUPITER's analog and DSP circuitry,
providing the two-way conversion
between 3“ IF and audio signals for both
receiver and transmitter. Іп the transmit
path, the U19 IC converts analog audio
input to digital data for the CPU and
converts digital-signal-processed СРО
data to analog 3" IF. In the receive path it
converts analog 3' IF signals to digital
data for the DSP and converts the
processed data to audio for receiver
output.
U4, an Analog Devices ADSP2181
processor clocked at 16.66 MHz by У1,
provides much of JUPITER's
functionality. See Figure 4-13. Here the
selectivity-critical filtering, multiple-mode
modulation and demodulation, and
interpretation of operator input to the radio
controls takes place. Buffers, US and 09,
are the drivers for discrete control signals
to the RF board and U9 also conditions
digital lines from such external control
inputs as MIC_PTT (push-to-talk) and
CW_KEY_R (Ring) and CW_KEY_T
(Тр). US digitizes analog control signals
from the transmitter and receiver. These
include FwdPwr and RefPwr from the
5-4
transmitter and AGC from the receiver.
U4 processes these inputs and returns
analog control outputs via the D/A
converter at U7 output. U22 is a serial
Read-Only Memory that stores
configuration data for the processor. U10
is the Flash Random-Access-Memory that
holds the operating data and control
settings. 1018 performs parallel-to-serial
and serial-to-parallel data conversion
between the CPU and Jupiter's SERIAL
INTERFACE connector.
Subsidiary to the Sheet5 CPU schematic
diagram is the Sheet 6 PLD schematic.
The Programmable Logic Device, U20,
uses a single IC to replace many smaller-
scale digital ICs. It communicates with
the processor via 5 address lines and 8
data lines, and its internal logic handles six
VO connectors that serve the:
е 28154 GRAPHIC DISPLAY (766);
е 881887 KEYPAD (7Р7);
е ACC2 Connector (ЈРЗ),
e Amplifier Control Connectors (19);
and
e Factory Test Connectors (JP12) &
(P11);
The PLD section of the Logic board
schematic (Figure 4-14) shows the voltage
regulator, 1021, dedicated to the
GRAPHIC DISPLAY and 05, the driver
for its contrast signal.
5.4.3. Lowpass Filter - P/N 81863
This circuit board (Figure 4-17) accepts
band-selection signals from the. CPU via
driver, 01, in order to interpose the
appropriate low-pass filter between the
broadband 81896 Power Amplifier and the
antenna. These filters suppress
transmitter harmonics and undesired mixer
products to levels that satisfy FCC
requirements for signal purity and make
JUPITER a good RF neighbor.
74269 Second Printing
JUPITER. Model 538
30 August 2001