Texas Instruments MSP430x1xx - Page 100

Instruction Set
3-64
RISC 16−Bit CPU
* SETN Set negative bit
Syntax SETN
Operation 1 −> N
Emulation BIS #4,SR
Description The negative bit (N) is set.
Status Bits N: Set
Z: Not affected
C: Not affected
V: Not affected
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.