Texas Instruments MSP430x1xx - Page 101

Instruction Set
3-65
RISC 16−Bit CPU
* SETZ Set zero bit
Syntax SETZ
Operation 1 −> Z
Emulation BIS #2,SR
Description The zero bit (Z) is set.
Status Bits N: Not affected
Z: Set
C: Not affected
V: Not affected
Mode Bits OSCOFF, CPUOFF, and GIE are not affected.