Texas Instruments MSP430x1xx - Page 66

Instruction Set
3-30
RISC 16−Bit CPU
* CLR[.W] Clear destination
* CLR.B Clear destination
Syntax CLR dst or CLR.W dst
CLR.B dst
Operation 0 −> dst
Emulation MOV #0,dst
MOV.B #0,dst
Description The destination operand is cleared.
Status Bits Status bits are not affected.
Example RAM word TONI is cleared.
CLR TONI ; 0 −> TONI
Example Register R5 is cleared.
CLR R5
Example RAM byte TONI is cleared.
CLR.B TONI ; 0 −> TONI