System Control
Note:
Because there is a write buffer in the Cortex-M4 processor, it may take several clock cycles
before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt
source be cleared early in the interrupt handler (as opposed to the very last action) to avoid
returning from the interrupt handler before the interrupt source is actually cleared. Failure to
do so may result in the interrupt handler being immediately reentered (because the interrupt
controller still sees the interrupt source asserted).
Returns:
None.
18.2.1.10 ROM_SysCtlIntDisable
Disables individual system control interrupt sources.
Prototype:
void
ROM_SysCtlIntDisable(uint32_t ui32Ints)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13].
ROM_SysCtlIntDisable is a function pointer located at ROM_SYSCTLTABLE[14].
Parameters:
ui32Ints is a bit mask of the interrupt sources to be disabled. Must be a logical OR of
SYSCTL_INT_PLL_LOCK, SYSCTL_INT_CUR_LIMIT, SYSCTL_INT_IOSC_FAIL,
SYSCTL_INT_MOSC_FAIL, SYSCTL_INT_POR, SYSCTL_INT_BOR, and/or
SYSCTL_INT_PLL_FAIL.
Description:
Disables the indicated system control interrupt sources. Only the sources that are enabled can
be reflected to the processor interrupt; disabled sources have no effect on the processor.
Returns:
None.
18.2.1.11 ROM_SysCtlIntEnable
Enables individual system control interrupt sources.
Prototype:
void
ROM_SysCtlIntEnable(uint32_t ui32Ints)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_SYSCTLTABLE is an array of pointers located at ROM_APITABLE[13].
ROM_SysCtlIntEnable is a function pointer located at ROM_SYSCTLTABLE[13].
204 April 8, 2013
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