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Texas Instruments Tiva TM4C123GH6PM User Manual

Texas Instruments Tiva TM4C123GH6PM
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Flash
8 Flash
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.1 Introduction
The flash API provides a set of functions for dealing with the on-chip flash. Functions are provided
to program and erase the flash, configure the flash protection, and handle the flash interrupt.
The flash is organized as a set of 1 kB blocks that can be individually erased. Erasing a block
causes the entire contents of the block to be reset to all ones. These blocks are paired into a
set of 2 kB blocks that can be individually protected. The blocks can be marked as read-only or
execute-only, providing differing levels of code protection. Read-only blocks cannot be erased or
programmed, protecting the contents of those blocks from being modified. Execute-only blocks can-
not be erased or programmed, and can only be read by the processor instruction fetch mechanism,
protecting the contents of those blocks from being read by either the processor or by debuggers.
The flash can be programmed on a word-by-word basis. Programming causes 1 bits to become 0
bits (where appropriate); because of this, a word can be repeatedly programmed so long as each
programming operation only requires changing 1 bits to 0 bits.
The timing for the flash is automatically handled by the flash controller. In order to do this, the
flash controller must know the clock rate of the system in order to be able to time the number of
micro-seconds certain signals are asserted. The number of clock cycles per micro-second must be
provided to the flash controller for it to accomplish this timing.
The flash controller has the ability to generate an interrupt when an invalid access is attempted
(such as reading from execute-only flash). This can be used to validate the operation of a program;
the interrupt will keep invalid accesses from being silently ignored, hiding potential bugs. The flash
protection can be applied without being permanently enabled; this, along with the interrupt, allows
the program to be debugged before the flash protection is permanently applied to the device (which
is a non-reversible operation). An interrupt can also be generated when an erase or programming
operation has completed.
8.2 Functions
Functions
int32_t ROM_FlashErase (uint32_t ui32Address)
void ROM_FlashIntClear (uint32_t ui32IntFlags)
void ROM_FlashIntDisable (uint32_t ui32IntFlags)
void ROM_FlashIntEnable (uint32_t ui32IntFlags)
uint32_t ROM_FlashIntStatus (bool bMasked)
int32_t ROM_FlashProgram (uint32_t pui32Data, uint32_t ui32Address, uint32_t ui32Count)
tFlashProtection ROM_FlashProtectGet (uint32_t ui32Address)
int32_t ROM_FlashProtectSave (void)
int32_t ROM_FlashProtectSet (uint32_t ui32Address, tFlashProtection eProtect)
April 8, 2013 73
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Texas Instruments Tiva TM4C123GH6PM Specifications

General IconGeneral
CoreARM Cortex-M4F
Clock Speed80 MHz
Flash Memory256 KB
SRAM32 KB
GPIO Pins43
UART8
I2C2
SPI/SSI4
USBUSB 2.0
Timers6
Communication InterfacesUART, I2C, SPI, USB
Operating Temperature-40°C to 85°C
PackageLQFP64

Summary

Boot Loader

Introduction

Explains the ROM-based boot loader and its interfaces for flash updates.

Serial Interfaces

Details the UART, SSI, and I2C interfaces used by the boot loader.

USB Interface

Describes the USB boot loader functionality using the DFU protocol.

Controller Area Network (CAN)

Flash

GPIO

Hibernation Module

Inter-Integrated Circuit (I2C)

Interrupt Controller (NVIC)

Memory Protection Unit (MPU)

Pulse Width Modulator (PWM)

Synchronous Serial Interface (SSI)

System Control

Timer

UART

uDMA Controller

USB Controller

Watchdog Timer

Functions

Lists and describes API functions for watchdog timer configuration, interrupts, and lock mechanism.

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