Interrupt Controller (NVIC)
13 Interrupt Controller (NVIC)
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
13.1 Introduction
The interrupt controller API provides a set of functions for dealing with the Nested Vectored Inter-
rupt Controller (NVIC). Functions are provided to enable and disable interrupts, register interrupt
handlers, and set the priority of interrupts.
The NVIC provides global interrupt masking, prioritization, and handler dispatching. Thirty-two in-
terrupt sources and eight priority levels are supported. Individual interrupt sources can be masked,
and the processor interrupt can be globally masked as well (without affecting the individual source
masks).
The NVIC is tightly coupled with the Cortex-M4 microprocessor. When the processor responds
to an interrupt, NVIC will supply the address of the function to handle the interrupt directly to the
processor. This eliminates the need for a global interrupt handler that queries the interrupt controller
to determine the cause of the interrupt and branch to the appropriate handler, reducing interrupt
response time.
The interrupt prioritization in the NVIC allows higher priority interrupts to be handled before lower
priority interrupts, as well as allowing preemption of lower priority interrupt handlers by higher prior-
ity interrupts. Again, this helps reduce interrupt response time (for example, a 1 ms system control
interrupt is not held off by the execution of a lower priority 1 second housekeeping interrupt handler).
Sub-prioritization is also possible; instead of having N bits of preemptable prioritization, NVIC can
be configured (via software) for N - M bits of preemptable prioritization and M bits of subpriority. In
this scheme, two interrupts with the same preemptable prioritization but different subpriorities will
not cause a preemption; tail chaining will instead be used to process the two interrupts back-to-
back.
If two interrupts with the same priority (and subpriority if so configured) are asserted at the same
time, the one with the lower interrupt number will be processed first. NVIC keeps track of the nesting
of interrupt handlers, allowing the processor to return from interrupt context only once all nested
and pending interrupts have been handled.
13.2 Functions
Functions
void ROM_IntDisable (uint32_t ui32Interrupt)
void ROM_IntEnable (uint32_t ui32Interrupt)
uint32_t ROM_IntIsEnabled (uint32_t ui32Interrupt)
bool ROM_IntMasterDisable (void)
bool ROM_IntMasterEnable (void)
void ROM_IntPendClear (uint32_t ui32Interrupt)
April 8, 2013 137
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