Toshiba MM20E45 - Page 30

5-7
4. SYNC SIGNAL PROCESSING CIRCUIT
This circuit also employs ICH01, the same as Mode discriminating circuit.
Posi Non
Neg
H.Pol.
Posi Non
Neg
Posi Non
Neg
V.Pol.
Posi Non
Neg
Neg
H.State
Non
Neg
Posi
Neg
V.State
Non
Neg
Posi
20 19 18 17 16 15 14 13 12 11
Digital Vcc
(5~12V)
GND
Vert
S/S
IN
Digital
GND
VD
Out
HD
Out
HD
Out
VDHDHD
+
Vcc
12V
Clamp
Clamp
Out
Clamp
Timing
Clamp
Gen.
Edge
SW
V.Sync
Sep.
10
9876
Vert.
Det
Vert.
Shape
Hor.
Det
Hor.
Shape
5432
Sync
Sep.
1
Logic
Logic
Green
Sep
Filter
Green
IN
Green
GND
Comp/H
Comp/H
Det
H.Det
Vert
Comp/H
IN
Vert
IN
Vert
Det
Vert
S/S
Adj
Table-6. Priority order of output
Sync signals are input as follows; TTL level hor sync or
composite sync to pin 6, TTL level ver sync to pin 8, and Sync
On Green sync to pin 4. Output signals are as follows;
Positive ver sync at pin 13, Positive hor sync at pin 14 and
Negative hor sync at pin 15.
When plural sync signals are at the same time input, the
priority order is decided as in Table-6.
Fig. 7
Input signal (pin) Output signal (pin)
pin 4 pin 6 pin 8
pin 14
pin 15
pin 13 pin 17
O
O
O
O
X
X
X
X
X
O
X
O
X
O
X
O
X
X
O
O
X
X
O
O
4
6
4
6
X
6
X
6
11
11
6
8
X
11
8
8
4
6
4
6
X
6
X
6