13-5
2-2-3 Partial Resonant Circuit
A charging current flows from ND winding to C3 connected
to IOS terminal (pin 4) through RQ10, RQ09, RQ08, DQ04,
LQ04 for the off period as shown in Fig. 13-11.
C3
voltage
across
O.S.C
Output
Resonant
voltage
V
DS
ID
0.75V
t
Fig. 13-9
However, the voltage is higher than the IOS threshold voltage
of 0.75V, the over current protection circuit is not released
immediately, but after the period it lowers than the 0.75V,
and the oscillator output is inverted and the MOS FET Tr1 is
also turned on.
For this period, a resonance occurs with a transformer LP and
CQ09 (2p
LC
), and CQ12 controls delay time of the on
time for the transistor, thereby setting a parameter for the
bottom point of the resonant voltage and reducing on-loss
considerably in addition to reduction of switching noises.
Fig. 13-10
DQ03 works as a clamp diode to suppress a negative charge
voltage of the integration circuit consisting of RQ10, RQ09,
and CQ12, CQ13 and CQ11 are noise suppression capacitors.
O.S.C Output
V
DS
ID
Fig. 13-11 Conventional circuit
Conventional
circuit
Partial resonant
circuit
On loss Off loss
Fig. 13-12 Loss
QQ01
1
2
4
3
C3
CQ13
CQ09
RQ10
RQ09
CQ12
DQ03
CQ11
RQ08
DQ04
LQ04
RQ06RQ05
RQ07
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