13-6
2-2-4 Drive Circuit
The drive circuit accepts the pulse signal from the oscillator
and charges and discharges the gate-source capacitor of the
power MOS FET.
2-2-6 Latch Circuit
The latch circuit is provided to protect QQ01. That is, when
the voltage at VIN terminal increases excessively and QQ01
temperature rises excessively due to some reasons, the latch
circuit keeps the oscillator output at a low level and stops
operation of the power circuit.
If the latch circuit is in operation, voltage regulator (Reg.)
circuits inside the control circuit is working and the circuit
current is in high condition. As a result, the VIN terminal
voltage is rapidly dropped. When the VIN terminal voltage
lowers by less than the operation stop voltage (10V TYP.),
the circuit current becomes less than 400 µA, so the VIN
terminal voltage starts increasing.
And when the VIN terminal voltage reaches the operation
start voltage (16V TYP.), the circuit current increases again
and the VIN terminal voltage drops.
In this way, when the latch circuit is operating, the VIN
terminal voltage increases and decreases between 10V TYP.
and 16V TYP., thereby preventing the VIN terminal voltage
from excessive increase or protecting QQ01. Fig. 13-16
shows VIN terminal waveforms when the latch circuit is
working.
Releasing of the latch circuit is conducted by lowering the
VIN terminal voltage to a value less than 6.5V. Generally, the
AC power is turned off once and then restart.
Fig. 13-15 VIN terminal waveform when
working the latch circuit
Fig. 13-13 Drive circuit
2-2-5 IOS Terminal (pin 4), O.C.P. (Over Current
Protection) Circuit
Drain current detection for the MOS FET is carried out by
connecting RQ05, RQ06 between the MOS FET source
terminal (pin 2) and GND (pin 3) and by feeding the voltage
drop to the IOS terminal. The threshold voltage of the IOS
terminal is set to about 0.75V from
the ground at TC = 25°C.
RQ07 and C3 work as a filter to prevent erroneous operation
due to a surge current caused when the MOS FET is turned
on.
O.C.P.
D
S
RQ07
RQ05 RQ06
1K
los
C3
2
4
3
1
GND
Fig. 13-14 Overcurrent detection circuit
Drive
From
OSC output
From regulator
1
2
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