voltage level at the positive input of op-amp IC14-A, the output of which turns on fan drive transistor
Q38. The fan current is monitored by R120, R121 and amplified by IC14-B to provide negative
feedback to the negative input of IC14-A.
Secondary Side
The main secondary winding is centre tapped and terminates on pins 19/20, 15/16 with the centre
tap on 17/18.
Snubber networks R7, C13 and C14, R18 across each half reduce high frequency ringing.
D47 and C80 generate a negative rail which bleeds a negative current from the output via resistors
R131 and R132.
The voltage on the secondary winding is rectified by D47 & D11, L-C filtered by L1, C5, C7, C8, C11
with flywheel diodes D6 & D7, and fed to a linear output stage comprised of MOSFETs Q3, Q4, Q5,
Q6. To minimise power dissipation in the linear output stage, the voltage across the MOSFETs is
monitored by error amplifier IC7-A (Sheet 2) which maintains the voltage across the linear output
MOSFETs to below 1V by adjusting the ‘Control’ signal to the synchronous post regulator MOSFETs
drive circuit (Sheet 3).
The synchronous post regulator MOSFETs Q2 and Q8 regulate the voltage across the linear output
MOSFETs by initially blocking the pulse from the secondary winding and only conducting after a
delay determined by the ‘Control’ signal.
Referring to Sheet 3, the drive to the post regulator MOSFETs is generated by two identical circuits
operating in anti-phase.
An auxiliary centre tapped winding on the converter transformer T1 terminated on pins 21, 22, 23,
and 24 generates the V+SEC and –8VSEC rails for the secondary control circuitry and also the
reference pulses AAA and BBB for the post regulator control circuit.
This description refers to the upper channel on sheet 3.
The reference pulse AAA is buffered and squared by AND gate IC10-B. The output of the AND gate
charges and discharges capacitor C58 via R66. The discharge time is shorter due to R69 and D41
conducting. The resultant triangular waveform is shown in photograph 03.
The long tail pair (LTP) comparator Q22 & Q23 switches when the triangle waveform at Q23 base
exceeds the reference voltage on Q22 base. The ‘Control’ voltage from IC7-A is fed to the base of
Q21 via R75 and VR3. The pulse width of the two sides is balanced by adjusting VR3.
Q21 emitter sets a pedestal level from which the charging of C58 begins.
The higher this pedestal level, the quicker C58 charges to the reference level on Q22 base and the
LTP comparator switches. This in turn switches Q20 which delivers a pulse to AND gate IC10-D
where it is gated with the AAA reference signal, the trailing edge of which has been slightly delayed
by R71 and C59.
The output of the AND gate IC10-D drives a MIC4428 driver IC, the antiphase outputs of which drive
the gate of the synchronous post regulator MOSFET Q2 via gate drive transformer T4.
Photograph 04 shows the triangular signal at the base of Q23 together with the pulse at IC10-D
pin 9. The reference voltage at the base of Q22 is coincident with the X-axis in the centre of the
oscilloscope screen.
To avoid uncontrolled post regulator conduction, Q32 and associated components ensure that the
‘Control’ signal is clamped to 0V during initial power-up.
The constant power limit is realised using analogue multiplier IC6.
The output voltage and output current are monitored by IC5-A and IC5-B respectively and the
resultant signals fed to the Y and X inputs of the analogue multiplier. The output of the multiplier is
of the form (X*Y)/10 +Z.
Z is a third input and is used to modify the power limit to give a lower power limit at high output
current. The correction signal is generated by IC15-B.
12
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