TTI QPX600D - Page 31

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The Limit Event Status Register is read and cleared by the LSR<n>? command. The Limit Event
Status Enable Register is set by the LSE<n> <nrf> command and read by the LSE<n>? command.
Bit 7 -
Reserved for future use
Bit 6 -
Set when a fault trip has occurred which requires AC power OFF/ON to reset.
Bit 5 -
Set when an output sense trip has occurred
Bit 4 -
Set when an output over current trip has occurred
Bit 3 -
Set when an output over voltage trip has occurred
Bit 2 -
Set when output enters power limit (unregulated mode)
Bit 1 -
Set when output enters current limit (constant current mode)
Bit 0 -
Set when output enters voltage limit (constant voltage mode)
Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request Enable
Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating a
Service Request on the bus.
The Status Byte Register is read either by the *STB? command, which will return MSS in bit 6, or
by a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the
*SRE <nrf> command and read by the *SRE? command.
Bit 7 - Not used.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting
Service message and the Master Status Summary message. RQS is returned in
response to a Serial Poll and MSS is returned in response to the *STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a response
message formatted and ready to send to the controller. The bit will be cleared after the
Response Message Terminator has been sent.
Bit 3 - Not used.
Bit 2 -
Not used.
Bit 1 - LIM2. This will be set if any bits in the Limit Event Status register for output2 are set and
corresponding bits are set in the Limit Event Status Enable register LSE2.
Bit 0 -
LIM1. This will be set if any bits in the Limit Event Status register for output1 are set and
corresponding bits are set in the Limit Event Status Enable register LSE1.