SARA-R4/N4 series - System Integration Manual
UBX-16029218 - R11 Design-in Page 108 of 157
☞ Capacitance and series resistance must be limited on the bus to match the I
2
C specifications (1.0 µs is
the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible.
☞ ESD sensitivity rating of the DDC (I
2
C) pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
☞ If the pins are not used as DDC bus interface, they can be left unconnected.
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