APC
(Automatic
Power
Control)
RF
power
output
from
final
amplifier
Q6003 (M67741
H)
is
sampled
by
C6023
and
delivered to detector
diode
D6003(1SS319)
where it is rectified. The resulting DC voltage
then passes
to
the REG Unit (DET). There the
APC voltage is fed
through
buffer amplifier
Q7003-1 (NJM2902M) to comparator Q7003-4
(NJM2902M) where the voltage is compared
with
a
reference
voltage
from
the
CPU
(POWER
REF)
to
produce
a control voltage
for the Automatic
Power
Controller Q6005
(2SB1134R)
on
the
PA
Unit,
which
regulates
supply
voltage to
RF
power
module
Q6003,
to maintain stable
high
or
low
output
power
under
varying
antenna
loading conditions.
CNTL-l
Unit
CNTL-l
Unit
consists
of
8-bit CPU QI008
(M38063EGP),
256-kByte EPROM
QI015
(TMS27C256), EEPROM Q1002 (BR93C56),
and
various analog switches. Microprocessor
operational code is stored
in
QI015, while
channel
and
optional data,
and
repeater con-
figuration information, is
programmed
from
an
external PC
at
4800 bits/sec. connected to
J2008
on
CNTL-2 Unit,
and
stored
in
QI002
via
programming
cable connection to
J2008
on
CNTL
Unit
2.
The
output
from
CPU
QI008
contains
three-line serial control
data
(DATA,
CLOCK
& ENABLE)
used
for
repeater/base
mode
control,
TX
and
RX
PLL data,
and
to control
analog
switch
Q2004
(NJU4066-BM)
on
CNTL-2 Unit.
Crystal
XI001 oscillates
at
4.9152 MHz,
and
provides stable clock timing
for
the
microprocessor.
When
the repeater is
powered
on,
the
voltage
at
pin
71
becomes
stable,
and
the
output
of voltage detector
IC
QI017 (QI008
pin
25-RST) becomes high, re-
setting the
CPU.
The CPU initialization routine loads the
operating
program
from RAM, frequency
and
other system
data
from Q1002. The CPU
then sends PLL
and
analog switch control
data
(J1001
pins
2, 3, &
4;
and
JI002 pins
2,
3
& 4), to
prepare
the
repeater for operation.
If
an
abnormal signal (such as PLL unlock
or
HI
TEMP) is detected
at
pin
2
or
pin
6 of the
CPU, CPU
pin
12
becomes low,
inhibit~g
transmission
by
disabling the
TX
voltage raIl.
Instruction
Manual
VXR-5000
Watch-Dog Timer
Watch-Dog Timer Q1018 (MC74HC4060F)
monitors
the
CPU for thrashing.
When
ab-
normal
CPU
operation
occurs, QI008,
pin
70
goes
low,
pulling
diode
OR
gate
DIOl8
(DAN202K),
which
in
turn
enables
the
pulse
train generated
by
QI018 to
be
input
to
pin
12.
QI018,
pin
1
then
outputs
a control pulse
to transistor driver
QI020 (FMG2),
which
in
turn
switches
the
output
of 5-V DC regulator
QI017 low, resetting microprocessor QI009
at
pin
25.
Three LEDs are
used
on
CNTL-l
Unit
for
TX
ALARM
and
AC indications.
The
TX
LED ,
indicates
the
repeater
is
transmitting,
the
ALARM LED
warns
of
four possible condi-
tions:
PLL unlock
(TX
&
RX),
high
final am-
plifier temperature,
EEPROM
prog~amming
data
loss
and
microprocessor thrashing.
CNTL-2
Unit
CNTL-2
Unit
contains
most
of
the
analog
switching gates
used
to control
the
various
repeater interconnections.
RX
&
TX
speech
audio is processed here.
Base Operation (TX,
line-input
audio)
Line
input
from J2001
pins
3 & 4 is .imped-
ance matched
by
transformer T2001,
then
de-
livered
to
audio
selector
Q2001
(MC14053BF). Line level
can
be
attenuated
by
switch 52001
and
line sensitivity can
be
adjusted to
-10
dB ±10 dBm
by
potentiometer
VR2001
to compensate for
audio
line level
variations.
Part
of this
audio
is amplified
by
Q2015 (TDA7233D) for local
speaker
output.
Line
audio
then
passes
through
analog
switch
Q2004-3 (NJU4066BM)
where
the
audio is pre-emphasized (+6dB/octave)
by
C2013 & R2018
and
Q2002-4 (NJM2902). The
audio
then
passes
through
IDC (instantane-
ous deviation control) amplifier
Q2003-1 (
NJM2902M).
Potentiometer
VR2002
sets
maximum
deviation. The signal is
then
am-
plified
by
Q2003-2 before passing
through
the
5-section active low-pass filter
formed
by
Q2003-4
and
Q200-3-3,
where
frequencies
above 3
kHz
are
attenuated
and
bandwidth
is
limited to
prevent
over-deviation.
2-3
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