ViewSonic VG181 - Page 15

ViewSonic Service Manual
July 2000 - Version 1.0 VG181
THEORY OF CIRCUIT OPERATION
The PW364 sets PORTB3 (ASYOE) to a high state that will allow 74LCX125 (U10)
to output the GHS and GVS signals which are then detected at GHS! (pin 13) and
RVSI (pin 14). When GHS and GVS are detected, the PW364 will configure the
registers of AD9884A to satisfy the operation through SCL and SDA of I°C bus.
Conversely, when PW364 sets PORTB3 (ASYOE) to a low state, the analog port is
disabled and the display is in the digital interface mode or power saving mode.
The AD9884A is an 8-bit, 140 Msps, monolithic analog interface for capturing RGB
graphics signals from personal computers and workstations. It includes +1.25V
reference, PLL to generate a pixel clock from Hsync, and programmable gain,
offset , and clamp circuits .
The functional block diagram of AD9884A is shown below:
RoutA
RoutB
GoutaA
GoutB
BoutA
BoutB
HSYNC 2 DATACK
COAST HSOUT
CLAMP
Generator
CKINV
CKEXT
&
2
Oo
es z & a @ « Fi
qQ > m A
= H uv
q o 3 ae A a
hy Oo 9 ind io
L3 ,2) =
1} Aa
Page 13
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