EasyManua.ls Logo

ViewSonic VG181 - Page 16

ViewSonic VG181
72 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Service
Manual
ViewSonic
VG181
July
2000
-
Version
1.0
THEORY
OF
CIRCUIT
OPERATION
If
the
user
changes
to
analog
mode
or
the
analog
port
is
reactivated
from
the
host
device,
then
the
PW364
will
set
PORTB3
(ASYOE)
and
PORTB2
(ADCOE)
to
high
states
to
enable
H-Sync,
V-Sync,
and
AD9884A.
The
PW364
will
change
the
PLL
division
ratio,
clock
phase,
VCO
range,
charge
pump
current,
etc.,
depending
on
the
timing
of
GHS
and
GVS.
The
action
should
be
fulfilled
through
SDA
and
SCL
of
the
I?C
bus
to
change
the
data
of
control
registers
of
AD9884A.
The
PLL
derives
a
master
clock
from
the
incoming
H-Sync
signal.
The
master
clock
frequency
is
then
divided
by
an
integer
value,
and
the
divider’s
output
is
phase-locked
to
H-
Sync.
The
PLL
characteristic
is
determined
by
the
loop
filter
design
which
is
controlled
by
PLL
charge
pump
current
(CURRENT)
and
VCO
range
setting
(VCORNGE).
The
values
of
VCO
range
and
charge
pump
current
are
shown
below:
_Voornge
|
oo
|
so
|
|
oo
|
100
20-60
50-90
10
80-120
11
110-140
|
100
|
so
|
tor
|
00
|
ant
|
1500
Whenever
the
contrast
or
brightness
of
the
analog
port
is
adjusted,
then
the
input
gain
or
input
offset
should
be
adjusted
through
the
IC
bus.
The
power
of
AD9884A
is
controlled
by
PORTB5
(PWAD)
of
Pw364
and
filtered
by
L22,
111,
L12
and
L13.
The
H-Syne
input
is
used
as
a
reference
to
generate
the
pixel
sampling
clock.
A
5-bit
value
(PHASE)
adjusts
the
sampling
phase
in
32
steps
across
one
pixel
time,
to
generate
a
stabie
timing
relationship
between
HSOUT
and
DATACK.
The
captured
analog
RGB
data
is
digitized
and
output
to
odd
and
even
data
channel
port
A
and
port
B.
The
output
data
is
aligned
to
the
leading
edge
of
HSOUT.
If
the
signal
of
sync
on
green
is
detected
by
SOGIN
then
the
SOGOUT
will
produce
a
digital
composite
sync.
Conversely,
if
the
analog
port
is
disabled,
then
PORTB3
(ASYOE)
and
PORTB2
(ADCOE)
of
PW364
will
be
in
the
low
state
setting
the
AD9884A
to
power
down
mode
and
all
outputs
of
AD9884<A
to
tristate
.
001
011
104
114
Page
14
Confidential
-
Do
Not
Copy

Related product manuals