ViewSonic VG181 - Page 20

Service Manual ViewSonic
VG181 July 2000 - Version 1.0
THEORY OF CIRCUIT OPERATION
The sync decoder detects and processes the horizontal sync (GHS), vertical syne
(GVS)
,
sync
on
green
(GSOG)
,
and
field
(GFIELD)
inputs
used
for
timing.
There
are
several
bits
to
indicate
the
status
of
the
inputs.
For
horizontal
sync,
HSOK=1
indicates
that
the
horizontal
line
rate
is
faster
than
10KHz.
For
vertical
sync,
VSOK=1 indicates that the vertical field or frame rate is faster than 10Hz. For sync
on green, SOGACT=1 indicates that transitions on GSOG are occurring faster than
10Hz.
The
PLL
control
block
generates
the
timing
signals
required
for
an
external
PLL.
GCOAST
is
an
output
used
to
tell
the
PLL
to
coast
during
vertical
blanking.
This
is
used
to
keep
the
PLL
from
making
spurious
change
due
to
extra
or
missing
HSYNC
pulses.
Output
GREF
is
a
polarity
corrected
delayed
version
of
the
active
horizontal
sync
signal
.
GREF
is
delayed
from
the
input
HSYNC
by
an
amount
specified
by
register
PHASE(7:0)
.
Changing
PHASE
will
change
the set
up
/hold
time relationship
between
the sample
clock
and the
data coming
into
the
external
ADC.
Output GHSFOUT is the field output signal used to tell an external ADC whether
even or odd pixels are being captured during half sample mode.
When EXTFCE=1 the external flow control is enabled, each new line is marked by
an
edge
on
the
GLAVIN
input
(pin
GFBK),
but
while
EXTFCE=0
the
GFBKINinput
(pin GFBK) is used as the input HSYNC signal for pixel counters.
Display port
The
display
port
processes
and
prepares
the
data
for
display.
The
output
data
is
sent
out
on
pins
DRE(7:0)
,
DGE(7:0)
,
DBE(7:0)
,
DRO(7:0)
,
DGO(7:0)
and
DBO(7:0)
that
is controlled
by
display
timing generator
.
The block diagram of display port is as follows :
Scaled
Display
Data
DRE[7: 0}
DGE[7:0}
DBE[7:0]
on
Screen
Display
Overlay
Ate DRO[7: 0}
ata
DGOI7:0}
DBO[7:0}
Display
Timing
Generator
DCKEXT
Page 18
Confidential - Do Not Copy
era A ae te RR