ViewSonic VG181 - Page 32

Service Manual ViewSonic
VG181
July
2000
-
Version
1.0
THEORY OF CIRCUIT OPERATION
Configuration Pin Description
|_Pin Name _| Pin No.| Type _|
— a
__ Description
ODCK Polarity. A low level selects normal ODCK output. A
high level (3.3V) selects inverted ODCK output.
All other outputs signals are not affected by this pin. They|
will maintain the same timing no matter the setting of
OCK_INV pin.
Pixel Select. A low level indicates one pixel (up to 24-bits)
per clock mode using QE[23:0}. A high level (3.3V)
indicates two pixels (up to 48-bits) per clock mode using
ge[23:0} for first pixel and QO[23:0] for second pixel.
Output Data Format. This pin controls clock output format.
A low level indicates that ODCK runs continuously for TFT
PANEL SUPPORT. A high level indicates that ODCK is
stopped (LOW) when DE is low for DSTN panel support.
Refer to the TFT and/or DSTN Signal Mapping application
- e¥
notes (Sil/AN-0007-A and Sil/AN-0008-A) for a table on
DFO
TFT or DSTN panel support.
STAG_OUT 7 A high level select normal simultaneous outputs on all odd
and even data lines. A tow level selects staggered output
drive. This function is only available in 2-pixels per clock
mode.
ST 3 Output Drive. A high level selects HIGH output drive
strength. A low level selects LOW output drive stength.
Power Management Pin Description
Sync Detect. A high level i is output when DE is actively
toggling indicating that the link is alive. A low level is output
when DE is inactive, indicating the link is down. Can be
connected to PDO to power the outputs when DE is not
detected. The SCDT output itself, however, remains in the
active mode at all times.
Output Driver Power Down (active low). A high level
indicates normal operation. A low level puts all the output
drivers only (except SCDT and CTL1) into a high
impedance (tri-state) mode. A weak internal pull-down
device brings each output to ground. PDO is a sub-sef of
the PD description. The chip is not in power-down mode
with this pin.
There is an internal pull-up resistor that defaults the chip to
normal operation if left unconnected. SCDT and CTL1 are
not tri-stated by this pin.
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