Xilinx Alveo U50

Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Card Features...............................................................................................................................7
Block Diagram..............................................................................................................................7
Design Flows................................................................................................................................ 9
Chapter 2: Vivado Design Flow..............................................................................10
Board Support Files for the Alveo U50 Card.......................................................................... 10
Creating an RTL Project Based on the U50 Board File..........................................................11
Creating an MCS File and Programming the Alveo Card..................................................... 12
Chapter 3: Card Installation and Configuration......................................... 14
Standard ESD Measures........................................................................................................... 14
Installing Alveo Data Center Accelerator Cards in Server Chassis......................................15
FPGA Configuration...................................................................................................................15
Chapter 4: Card Component Description........................................................ 16
UltraScale+ FPGA....................................................................................................................... 16
Quad SPI Flash Memory........................................................................................................... 16
Maintenance Connector Interface.......................................................................................... 17
PCI Express Endpoint................................................................................................................17
SFP-DD Module Connectors.....................................................................................................18
I2C Bus........................................................................................................................................18
Status LEDs.................................................................................................................................18
Card Power System................................................................................................................... 19
Appendix A: Xilinx Design Constraints (XDC) File...................................... 21
Appendix B: Regulatory and Compliance Information........................... 22
Safety Compliance.....................................................................................................................22
EMC Compliance........................................................................................................................22
CE Directives.............................................................................................................................. 23
UG1371 (v1.2) December 18, 2019 www.xilinx.com
Alveo U50 Accelerator Card User Guide 3
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