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Xilinx SelectIO 7 Series User Manual
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7 Series FPGAs
SelectIO Resources
User Guide
UG471 (v1.10) Ma
y 8, 2018
2
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
5
Preface: about this Guide
11
Guide Contents
11
Additional Resources
11
Chapter 1: Selectio Resources
13
I/O Tile Overview
13
New Features
14
Selectio Resources Introduction
15
Selectio Resources General Guidelines
17
Series FPGA I/O Bank Rules
17
Supply Voltages for the Selectio Pins
18
State of I/Os During and after Configuration
19
Series FPGA DCI-Only Available in the HP I/O Banks
19
Introduction
19
Xilinx DCI
20
Match_Cycle Configuration Option
21
Dciupdatemode Configuration Option
21
DCIRESET Primitive
22
Special DCI Requirements for some Banks
22
DCI Cascading
22
Controlled Impedance Driver (Source Termination)
25
Controlled Impedance Driver with Half Impedance (Source Termination)
25
Split-Termination DCI (Thevenin Equivalent Termination to VCCO/2)
26
VRN/VRP External Resistance Design Migration Guidelines
27
DCI and 3-State DCI (T_DCI)
28
DCI in 7 Series Fpgas I/O Standards
29
DCI Usage Examples
31
Series FPGA Selectio Primitives
34
IBUF and IBUFG
35
Ibuf_Ibufdisable
35
Ibuf_Intermdisable
36
IBUFDS and IBUFGDS
36
IBUFDS_DIFF_OUT and IBUFGDS_DIFF_OUT
37
Ibufds_Diff_Out_Ibufdisable
37
Ibufds_Ibufdisable
37
Ibufds_Intermdisable
38
Ibufds_Diff_Out_Intermdisable
38
Iobuf
39
Iobuf_Dcien
39
Iobuf_Intermdisable
40
Iobufds
41
Iobufds_Dcien
41
Iobufds_Diff_Out
42
Iobufds_Diff_Out_Dcien
43
Iobufds_Diff_Out_Intermdisable
44
Iobufds_Intermdisable
44
Obuf
45
Obufds
45
Obuft
46
Obuftds
46
Series FPGA Selectio Attributes/Constraints
46
DCI_CASCADE Constraint
46
Location Constraints
47
IOSTANDARD Attribute
47
IBUF_LOW_PWR Attribute
47
Output Slew Rate Attributes
48
Output Drive Strength Attributes
48
PULLUP/PULLDOWN/KEEPER Attribute for IBUF, OBUFT, and IOBUF
49
Differential Termination Attribute
49
Internal VREF
50
VCCAUX_IO Constraint
50
Series FPGA I/O Resource Vhdl/Verilog Examples
51
Supported I/O Standards and Terminations
51
LVTTL (Low Voltage TTL)
51
LVCMOS (Low Voltage CMOS)
54
LVDCI (Low-Voltage Digitally Controlled Impedance)
56
Lvdci_Dv2
57
HSLVDCI (High-Speed LVDCI)
59
HSTL (High-Speed Transceiver Logic)
60
HSTL_ I and HSTL_ I_18
60
HSTL_ II and HSTL_ II_18
60
HSTL_ I_DCI and HSTL_ I_DCI_18
60
Hstl_I_12
60
DIFF_HSTL_ II and DIFF_HSTL_II_18
61
DIFF_HSTL_I and DIFF_HSTL_I_18
61
DIFF_HSTL_I_DCI and DIFF_HSTL_I_DCI_18
61
HSTL_ II_DCI and HSTL_ II_DCI_18
61
HSTL_ II_T_DCI and HSTL_ II_T_DCI_18
61
DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18
62
DIFF_HSTL_II_T_DCI and DIFF_HSTL_II_T_DCI_18
62
HSTL Class I (1.2V, 1.5V, or 1.8V)
62
Differential HSTL Class I
64
HSTL Class II
66
Differential HSTL Class II
68
HSTL_II_T_DCI (1.5V or 1.8V) Split-Thevenin Termination (3-State)
72
SSTL (Stub-Series Terminated Logic)
74
Sstl15_R, Sstl135_R, Diff_Sstl15_R, Diff_Sstl135_R
76
Sstl18_I, Diff_Sstl18_I
76
Sstl18_I_Dci, Diff_Sstl18_I_Dci
76
Diff_Sstl15_T_Dci, Diff_ Sstl135_T_Dci
77
Sstl12, Sstl12_Dci, Sstl12_T_Dci, Diff_Sstl12, Diff_Sstl12_Dci, Diff_Sstl12_T_Dci
77
Sstl135_Dci
77
Sstl18_Ii_T_Dci, Sstl15_T_Dci, Sstl135_T_Dci, Diff_Sstl18_Ii_T_Dci
77
Sstl18, Sstl15, Sstl135, Sstl12
78
Differential SSTL18, SSTL15, SSTL135, SSTL12
80
SSTL18, SSTL15, SSTL135, or SSTL12 (T_DCI) Termination
84
HSUL_12 (High Speed Unterminated Logic)
84
HSUL_12 and DIFF_HSUL_12
84
HSUL_DCI_12 and DIFF_HSUL_12_DCI
85
Hsul_12
85
Differential HSUL_12
86
MOBILE_DDR (Low Power DDR)
88
Summary of Memory Interface Iostandards and Attributes Supported
88
LVDS and LVDS_25 (Low Voltage Differential Signaling)
91
Receiver Termination
91
Transmitter Termination
91
RSDS (Reduced Swing Differential Signaling)
94
Mini-LVDS (Mini Low Voltage Differential Signaling)
94
PPDS (Point-To-Point Differential Signaling)
95
TMDS (Transition Minimized Differential Signaling)
95
BLVDS (Bus LVDS)
96
Rules for Combining I/O Standards in the same Bank
97
Simultaneous Switching Outputs
104
Pin Planning to Mitigate SSO Sensitivity
104
Chapter 2: Selectio Logic Resources
105
Introduction
105
ILOGIC Resources
106
Combinatorial Input Path
109
Input DDR Overview (IDDR)
109
OPPOSITE_EDGE Mode
109
SAME_EDGE Mode
110
SAME_EDGE_PIPELINED Mode
110
Input DDR Resources (IDDR)
111
IDDR VHDL and Verilog Templates
112
ILOGIC Timing Models
113
ILOGIC Timing Characteristics
113
ILOGIC Timing Characteristics, DDR
113
Input Delay Resources (IDELAY)
115
IDELAYE2 Primitive
116
IDELAY Ports
117
IDELAY Attributes
119
IDELAY Modes
120
IDELAY Timing
121
IDELAY VHDL and Verilog Instantiation Template
123
Stability after an Increment/Decrement Operation
123
Idelayctrl
124
IDELAYCTRL Overview
124
IDELAYCTRL Ports
124
IDELAYCTRL Primitive
124
IDELAYCTRL Locations
125
IDELAYCTRL Timing
125
IDELAYCTRL Usage and Design Guidelines
126
OLOGIC Resources
126
Combinatorial Output Data and 3-State Control Path
127
Output DDR Overview (ODDR)
127
OPPOSITE_EDGE Mode
127
SAME_EDGE Mode
127
Clock Forwarding
128
Output DDR Primitive (ODDR)
129
ODDR VHDL and Verilog Templates
129
OLOGIC Timing Models
130
Timing Characteristics
130
Output Delay Resources (ODELAY)-Not Available in HR Banks
134
ODELAYE2 Primitive
134
ODELAY Ports
135
ODELAY Attributes
137
ODELAY Modes
138
ODELAY Timing
139
ODELAY VHDL and Verilog Instantiation Template
141
Stability after an Increment/Decrement Operation
141
Chapter 3: Advanced Selectio Logic Resources
143
Introduction
143
Input Serial-To-Parallel Logic Resources (ISERDESE2)
143
ISERDESE2 Primitive (ISERDESE2)
145
ISERDESE2 Ports
146
Registered Outputs - Q1 to Q8
146
Bitslip Operation - BITSLIP
147
Clock Enable Inputs - CE1 and CE2
147
Combinatorial Output - O
147
Divided Clock Input - CLKDIV
148
High-Speed Clock Input - CLK
148
High-Speed Clock Input - CLKB
148
Serial Input Data from IOB - D
148
High-Speed Clock for Strobe-Based Memory Interfaces and Oversampling Mode - OCLK
149
Reset Input - RST
149
Serial Input Data from IDELAYE2 - DDLY
149
Serial Input Data from OSERDESE2 - OFB
149
ISERDESE2 Attributes
150
DATA_RATE Attribute
151
DATA_WIDTH Attribute
151
INTERFACE_TYPE Attribute
151
NUM_CE Attribute
152
SERDES_MODE Attribute
152
ISERDESE2 Clocking Methods
152
NETWORKING Interface Type
152
MEMORY Interface Type
153
MEMORY_QDR Interface Type
153
OVERSAMPLE Interface Type
153
MEMORY_DDR3 Interface Type
155
ISERDESE2 Width Expansion
155
Guidelines for Expanding the Serial-To-Parallel Converter Bit Width
155
ISERDESE2 Latencies
156
Dynamic Clock Inversions
156
ISERDESE2 Feedback from OSERDESE2
156
Using D and DDLY in the ISERDESE2
157
ISERDESE2 Timing Model and Parameters
157
Timing Characteristics
157
ISERDESE2 VHDL and Verilog Instantiation Template
158
BITSLIP Submodule
158
Bitslip Operation
158
Bitslip Timing Model and Parameters
160
Output Parallel-To-Serial Logic Resources (OSERDESE2)
161
Data Parallel-To-Serial Converter
161
3-State Parallel-To-Serial Conversion
162
OSERDESE2 Primitive
162
OSERDESE2 Ports
163
Data Path Output - OQ
163
Output Feedback from OSERDESE2 - OFB
163
3-State Control Output - TFB
164
3-State Control Output - TQ
164
3-State Signal Clock Enable - TCE
164
Divided Clock Input - CLKDIV
164
High-Speed Clock Input - CLK
164
Output Data Clock Enable - OCE
164
Parallel 3-State Inputs - T1 to T4
164
Parallel Data Inputs - D1 to D8
164
Reset Input - RST
164
OSERDESE2 Attributes
165
DATA_RATE_OQ Attribute
166
DATA_RATE_TQ Attribute
166
DATA_WIDTH Attribute
166
SERDES_MODE Attribute
166
TRISTATE_WIDTH Attribute
166
OSERDESE2 Clocking Methods
166
OSERDESE2 Width Expansion
167
Guidelines for Expanding the Parallel-To-Serial Converter Bit Width
168
Output Feedback
168
OSERDESE2 Latencies
168
DEFAULT Interface Type Latencies
168
OSERDESE2 Timing Model and Parameters
169
Timing Characteristics of 2:1 SDR Serialization
170
Timing Characteristics of 8:1 DDR Serialization
171
Timing Characteristics of 4:1 DDR 3-State Controller Serialization
172
OSERDESE2 VHDL and Verilog Instantiation Templates
173
IO_FIFO Overview
173
In_Fifo
174
IN_FIFO Primitive
175
Out_Fifo
177
OUT_FIFO Primitive
178
Resetting the IO_FIFO
180
EMPTY and FULL Flags
180
ALMOST EMPTY and ALMOST FULL Flags
180
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Xilinx SelectIO 7 Series Specifications
General
Brand
Xilinx
Model
SelectIO 7 Series
Category
Computer Hardware
Language
English
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