Xilinx SelectIO 7 Series User Manual

7 Series FPGAs SelectIO Resources User Guide www.xilinx.com 183
UG471 (v1.10) May 8, 2018
Appendix A
Termination Options for
SSO Noise Analysis
The PlanAhead™ software has the ability to perform simultaneous switching noise (SSN)
analysis for each design, taking into account the actual I/O standards and options
assigned to the I/O pins in the target device and package. For details on how to use this
feature and perform the SSN analysis, see the “Using Noise Analysis Predictors” section of
UG632
: PlanAhead User Guide.
For each output pin, there is the option to specify whether or not termination is present on
the board. The off-chip termination field automatically populates with the default
terminations for each I/O standard, if one exists.
Table A-1 lists all of the default terminations for each of the I/O standards supported by
the 7 series FPGAs when using the SSN predictor tool within the PlanAhead™ software.
For each I/O pin in the design, the user can specify whether to use these terminations, or
to have no termination.
Table A-1: Default Terminations for SSN Noise Analysis by I/O Standard
IO Standard
(1)
Default Termination
HSTL_I Far V
TT
50Ω
HSTL_I_12 Far V
TT
50Ω
HSTL_I_18 Far V
TT
50Ω
HSTL_I_DCI Far V
TT
50Ω
HSTL_I_DCI_18 Far V
TT
50Ω
HSTL_II Near V
TT
50Ω & Far V
TT
50Ω
HSTL_II_18 Near V
TT
50Ω & Far V
TT
50Ω
HSTL_II_DCI Far V
TT
50Ω
HSTL_II_DCI_18 Far V
TT
50Ω
HSTL_II_T_DCI Far V
TT
50Ω
HSTL_II_T_DCI_18 Far V
TT
50Ω
HSUL_12 None
HSUL_12_DCI None
LVCMOS (all voltages)
LVTTL (2mA, 4mA, 6mA, and 8mA drive)
None
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Xilinx SelectIO 7 Series Specifications

General

Brand	Xilinx
Model	SelectIO 7 Series
Category	Computer Hardware
Language	English