Xilinx SelectIO 7 Series - Output Delay Resources (ODELAY)-Not Available in HR Banks

134 www.xilinx.com 7 Series FPGAs SelectIO Resources User Guide
UG471 (v1.10) May 8, 2018
Chapter 2: SelectIO Logic Resources
Output Delay Resources (ODELAY)—Not Available in HR Banks
Every HP I/O block contains a programmable absolute delay primitive called ODELAYE2.
The ODELAY can be connected to an OLOGICE2/OSERDESE2 block. ODELAY is a 31-tap,
wraparound, delay primitive with a calibrated tap resolution. Refer to the 7 series FPGA
data sheets for delay values. It can be applied to the combinatorial output path or
registered output path. It can also be accessed directly from the FPGA logic. ODELAY
allows outgoing signals to be delayed on an individual basis. The tap delay resolution is
varied by selecting an IDELAYCTRL reference clock from the range specified in the 7 series
FPGA data sheets.
ODELAYE2 Primitive
Figure 2-25 shows the ODELAYE2 primitive.
Table 2-13 lists the available ports in the ODELAYE2 primitive.
X-Ref Target - Figure 2-2 5
Figure 2-25: ODELAYE2 Primitive
C DATAOUT
INC
CE
CLKIN
ODATAIN
REGRST
LD
CINVCTRL
CNTVALUEIN[4:0]
LDPIPEEN
CNTVALUEOUT[4:0]
ODELAYE2
ug471_c2_23_0118
Table 2-13: ODELAYE2 Primitive Ports
Port
Name
Direction Width Function
C Input 1 Clock input used in VARIABLE, VAR_LOAD, or VAR_LOAD_PIPE mode.
REGRST Input 1 Reset to all zeroes for the pipeline register.
LD Input 1
Loads the ODELAY
primitive to the pre-programmed value in VARIABLE
mode. In VAR_LOAD mode, it loads the value of CNTVALUEIN. In
VAR_LOAD_PIPE mode, it loads the value currently in the pipeline register.
CE Input 1 Enable increment/decrement function.
INC Input 1 Increment/decrement number of tap delays.
CINVCTRL Input 1 Dynamically inverts the clock (C) polarity.
CNTVALUEIN Input 5 Input value from FPGA logic for dynamically loadable tap value.
CLKIN Input 1 Clock Access into the ODELAY (from the I/O CLKMUX).
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